XSPI Master IIP

• Compliant with XSPI protocol of JEDEC standard version 1.0 specification
• Supports single master and multiple slaves per interface port
• Supports Deep power down enter and exit commands
• Supports different lane modes:
• ->Single Lane mode
• ->Dual Lane mode
• ->Quad Lane mode
• ->Octal Lane mode
• Supports 1-bit wide SDR transfer
• Supports profile 1.0 Commands to manage a non-volatile memory device
• Supports profile 2.0 Commands to support read or write data for any time of slave
• devices
• Speed grades with data transfer rates up to
• ->400MT/s (200 MHz Clock)
• ->333MT/s (167 MHz Clock)
• ->266MT/s (133 MHz Clock)
• ->200MT/s (100 MHz Clock)
• Supports below protocol modes:
• ->1S - 1S -1S
• ->8D - 8D - 8D
• Data rate options in each phases S for SDR or D for DDR
• Transaction phases - Command, Address, Latency, Data
• Transfer bit width options in each phase W = 1 or 8
• Has inbuilt Host controller Interface (DMA Engine)
• Supports legacy SPI Devices on same device
• Supports Data Mask for write masking
• Supports Data strobe for read transaction
• Supports Auto Boot Mode
• Supports XIP/AIP Mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core Module interconnects all the sub-modules in the SPI IP. Ports of core module are the top level ports for the SPI IP.

PRESCALER: Prescaler Module is used to divide the system clock based on the given prescaler value to drive the serial clock input for SPI.

FSM: FSM Module generates the SPI transcations on SPI Master based on commands from CSR block. This blocks implements all the features of SPI specifications.

ARB: ARB Module implements the arbiter to arbit between HCI and FSM access to CSR block.

HCI: HCI Module implements SPI Host controller FSM. The HCI FSM fetches the data from descriptor memory like SPI commands and transmit data bytes and it loads sampled read data bytes into descriptor memory.

XIP: XIP Module implements XIP/AIP mode operation with zero software overhead. XIP Module consists of functionality of both XIP and AIP mode. In XIP (Xecute In Place mode) executing the code directly from the serial flash memory .It will directly read from the Flash memory.In AIP (Access In Place) mode has both read and write operation will execute.It will write data into the flash device.XIP module is connected with soc Slave interface.

BOOT: Boot Module allows the host to read the data from the flash device after the power is on or after the hardware reset is done. It reads the data from the flash device without read command and address

CSR: CSR Module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.