CORE: Core module interconnects all the sub-modules in the CXL IP. Ports of core module are the top level ports for the CXL IP.
CPI: CPI module handles the CPI FSM state flow and handles the inbound and outbound Cache/Mem informations.
TRANSACTION LAYER TRANSMITTER: Transaction layer transmitter stores the Cache/Mem informations from CPI in the Tx FIFO's and Handles the Tx credit flows.
LINK LAYER TRANSMITTER: Link layer transmitter packs the control Flits and packs the Cache/Mem informations into protocol flits and handles the retry mechanisms.
TRASACTION LAYER RECEIVER: Transaction layer receiver stores the Cache/Mem informations from Link layer in the Rx FIFO's and handles the Rx credit flows.
LINK LAYER RECEIVER: Link layer receiver decodes the control and protocol flits, And transmits the Cache/Mem informations to the Receiver transaction layer.
ALMP: This module responsible for almp packet generation and processes the received almp flits.
VLSM: VLSM module handles the cache/mem and CXL io VLSM states through the ALMP handshake.
ARBITER MUX: This module arbitrates between the cache/mem and cxl io flits to the physical layer.
ARBITER DEMUX: This module receives flits from physical layer and transmits to the Cache/Mem and cxl.io accordingly.
CXL IO DEVICE CORE: It coordinates and control interconnections between transmitter and receiver layers.
CXL IO TL TX: It handles TLP packing,flow control,VC management and optional ECRC integrity.
CXL IO TL RX: It processes received TLPs,Bad TLP packet discarding and receiver buffer handling.
CXL IO DL TX: Generates DLLPs like FC and ack/nack.It will add sequence number and LCRC to TLP and also handles replay mechanism.
CXL IO DL RX: It will process received TLPs and DLLPs.Schedules ACK/NACK for transmission.
CXL IO TX PHY: It will pack data,order sets,tokens and K characters.And handles scrambling,DC balance,tx lane reversal and tx pipeports. For flit mode it also includes flit packing,flit CRC,ECC/FEC integrity,flit replay mechanism.
CXL IO RX PHY: It will process received data and order sets,And handles descrambling,rx lane reversal,receive deskew and rx pipeports. For flit mode it also includes flit unpacking,flit validation using flit sequence number,CRC,ECC/FEC integrity checks,flit ack/nack scheduling.
CXL IO APP LAYER: It handles read and write requests between transaction layer and SoC interfaces.
CXL IO SYNCHRONIZER: This module is used to synchronize the signals which are crossing clock domains.
CDM: It has device capabilty and extended capability registers.
LBC: This module is used to access device capability and extended capability registers.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
