ARINC825 CONTROLLER IIP

Aeronautical Radio Incorporated 825 Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ARINC825 CONTROLLER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES

Implemented in Unencrypted Verilog, VHDL and SystemC
Supports with ARINC REPORT 825 - 2.
Supports Transmission data rates from 83.333 Kbps to 1Mbps.
Supports one-to-many communication and also peer-to-peer communication.
Supports all the four frame types.

Data frames
Remote frames
Error frames
Overload frames

Remote frame support.

Automatic transmission after reception of remote transmission request (RTR).
Automatic receive after transmission of an RTR.

Supports all the five types of error insertion and detection.

Bit errors
Stuff errors
CRC errors
Format errors
Acknowledgement errors

Tracks TEC/REC error counter and fault states.
Supports Bit by bit Arbitrations.
Glitch insertion and detection
Re-transmission of corrupted messages.
Monitors, detects and notifies the test bench of significant events such astransactions, warnings, and timing and protocol violations.
Supports constraints Randomization.
Callbacks in transmitter, receiver and monitor for various events.
Built in functional coverage analysis

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Arinc825 Controller IP. Ports of core module are the top level ports for the Arinc825 Controller IP.

TFSM: TFSM Module is responsible for driving Arinc825 frames through Bus. Standard and Extended Message formats transactions for both Arinc825 / Arinc825 FD frames. Response frame transactions, If remote frame was received.

RFSM: RFSM Module is responsible for sampling Arinc825 frames through Bus and also for Error detection.

TIMING: TIMING Module is responsible for Bit timing characteristics of Arinc825 protocol.and also for BRS(Bit rate switching) in Arinc825 FD Scenarios.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	12.95K	100MHz
TSMC 12nm	18.70K	100MHz
TSMC 90nm	18.66k	100MHz
TSMC 130nm	18.66K	100MHz
TSMC 180nm	19.82K	100MHz
GF 180nm	13.56K	100MHz
SMIC 40nm	13.83K	100MHz
UMC 55nm	22.21K	100MHZ

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	2158 LUT's	100MHZ

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.