INTERLAKEN IIP

• Compliant with Interlaken protocol specification v1.2
• Interlaken look as side protocol 1.1 Interlaken retransmission extension specification 1.2
• Interlaken Reed-Solomon Forward Error Correction Extension 1.1
• Interlaken Interoperability Recommendations 1.11 Interlaken Dual Calendar Extension 1.0
• Supports up to 1000Gbps Supports single channel and multichannel (up to 4 channel) Supports 256 communications channels, or up to 64K with channel extension
• Supports configurable number of lanes from 1 to 64 lanes
• Supports configurable burst max, burst short and meta-frame length.
• Supports the In-bound/out-bound flow control
• Supports burst interleaved and Packet mode Supports 80,64,40,32, 20,16,10 and 8 bit per lane serdes interface
• Supports 64/67 encoding and decoding with DC balance Supports automatic word and lane alignment Supports self-synchronizing data scrambler Supports status messaging Supports ILA overhead insertion and extraction Supports CRC32 generation and checking for lane data integrity Supports transmit and receive clock and data rate decoupling with programmable asynchronous FIFO
• Supports unidirectional and bidirectional operation Supports lane protection Supports test pattern generation and checker
• A simple control word structure to delineate packets, similar in function to SPI4.2 Optional support for scheduling enhancement to avoid unused bandwidth by using decision algorithm
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors
• This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

CORE: Core module interconnects all the sub-modules in the Ethernet 25G MAC IIP . Ports of core module are the top level ports for the Ethernet 25G MAC IIP.

TX MAC: The TX-MAC converts the incoming data stream into smaller Bursts (typically 64 or 256 bytes) and ensures that no single channe starves the others by interleaving packets from different logical channels and calculate a 24-bit CRC for each data to provide end-to-end data integrity across the link.

TX PCS: The TX-PCS converts the 64-bit data words into 67-bit blocks.The additional 3 bits are used to differentiate between Data and Control characters and a self synchronizing or side stream scrambler is used to the 64-bit payload to ensure DC balance

RX MAC: The RX-MAC collects the data word from all aligned lanes and reassembles and verifies the CRC of each incoming data stream. If a CRC mismatch if found, it flags an error to the user logic.

RX PCS: The Rx-PCS scans the incoming bitstream on each lane to identify the 67-bit boundaries by framing the bits. By identifying the 67-bit boundaries and it uses the descrambler to recover the original 64-bit data and then decodes the 67-bit data blocks back into 64-bit data and identifies whether the block is a Data or a control word.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.