CXS to UCIe Bridge IIP

• Supports specification version 1.0, 1.1, 2.0 and 3.0
• Supported Mode – Endpoint, Root Complex
• Supported Package - Standard package, Advanced Package
• Supported Protocol - CXS
• Supported Flit Format
• Raw Format
• 68B Flit Format
• Standard 256B End Header Flit Format
• Standard 256B Start Header Flit Format
• Latency-Optimized 256B without Optional Bytes Flit Format
• Latency-Optimized 256B with Optional Bytes Flit Format
• Supports 4 GT/s, 8 GT/s, 12 GT/s, 16 GT/s, 24 GT/s, 32 GT/s, 48 GT/s and 64GT/s speeds with
• 500 MHz, 1 GHz, 1.5 GHz, 2 GHz, 3 GHz, 4 GHz, 6GHz and 8 GHz UCIe clock frequency
• Supports 800 MHZ speed for sideband data
• Supports 16 Lanes, 32 Lanes and 64 Lanes
• Supports Sideband messaging for link training and parameter exchange
• Supports Sideband Mailbox Mechanism for read and write configuration
• Supports Clock gating Mechanism
• Supports all handshake mechanism
• Supports Data Link Feature Exchange
• Supports Link Power Management
• Supports Multi Stack protocol
• Supports all Vendor defined Sideband messages
• Supports UCIe Retimers
• Supports Flit Retry Mechanism
• Supports Flits CRC
• Compliant with the latest ARM AMBA CXS specification.
• Supports credit exchange mechanism.
• Supports Link activation and deactivation.
• Support for skipping link activation.
• Configurable credit mechanism including dynamic and pre-allocated credit control.
• Support for Interface properties and possible options as per protocol.
• Supports continuous delivery of data - uninterrupted transmission of packets.
• Fine grain control of below:
  • Flit packets placement
  • Packet control fields
• Ability to configure the width of all signals.
• Support for error injection during Link activation and deactivation.
• Ability to inject and detect errors including:
  • Credit exchange mechanism
  • Parity
  • Packet size
  • Link activation and deactivation
• Programmable Protocol signal delays.
• Supports constrained randomization of protocol attributes.
• Programmable Timeout insertion.
• Rich set of configuration parameters to control CXS functionality.
• Supports Positive edge clocking and no internal tri-states.
• Scan test ready.
• Fully synthesizable
• Static synchronous design
• Simple interface allows easy connection to microprocessor/ microcontroller devices

CORE: Core module interconnects all the sub-modules in the CXS to UCIe Bridge IP. Ports of core module are the top level ports for the CXS to UCIe Bridge IP.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ATU: Address translation unit Module translates the UCIe address to csr address.

Protocol layer: Protocol layer module performs APB to UCIe bridge connection to transfer sideband data in UCIe sideband packet formats.CXS UCIe Bridge is responsible for transmitting and receiving CXS data as mainband data.It converts incoming data into negotiated flit format and vice versa.

D2D adapter: The Die to Die Adapter (D2D) module interacts with Protocol Layer through FDI Mainband and Sideband signals and also interacts with Remote Die through RDI Mainband and Sideband signals.It facilitates data transfer from Protocol Layer to Remote Die and vice versa.During Active state, capability exchanges takes place and finalized capabilities are advertised in this module.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.