The SivaKali Tech CXPI SLAVE IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with ISO/WD 20794 CXPI Specification
Supports Data with clock is received on a single communication bus
Supports Maximum baud rate of 20 kbps.
Supports Wakeup pulse detection
Supports bus access method
Event Trigger method
Polling method to support periodic schedules
Supports Data signal encoding and decoding formats
Non-return to zero (NRZ) mode
Pulse width modulation (PWM) mode
Supports 8-bit CRC for normal frame and 16-bit CRC for long frame
Supports Error detection and Timeout detection
Supports 128x bit time oversampling
Supports programmable clock frequency up to 100 MHz
Supports CXPI status management
Supports Up to 16 nodes connected to a CXPI communication bus
Low cost single-wire implementation
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the CXPI Slave IP. Ports of core module are the top level ports for the CXPI Slave IP.
CSR: CSR module has all the Control and status registers. This module has RX FIFO for store response frame from slave. Has TX FIFO for transmit Header and data. This block contains interrupt enable and status registers.
APPS: Apps module implements and controls application/transport/network layer. Implements CRC logic, retry logic and Sleep/Wakeup. This block controls transmit and receive FSM.
TFSM: This block implements the UART transmit statemachine and PWM encoder. Also this block checks the collosion.
RFSM: This block implements the UART receive state machine and PWM decoder.
PRESCALER: Prescaler Module is used to divide the i_clk clock based on the given prescaler value to derive the serial clock for transmission and sampling of the frame. The clock divider is fractional clock divider.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 12nm
13.5K
50MHz
TSMC 28nm
9K
50MHz
TSMC 90nm
13.60K
50MHz
TSMC 130nm
13.59K
50MHz
TSMC 180nm
14.50K
50MHz
UMSC 55nm
17K
50MHz
SMIC 40nm
9.62K
50MHz
GF 180nm
9.63K
50MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
1500 LUT's
50MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
