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PCI Master Slave IIP

PCI Master Slave IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech PCI Master Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Enabling next-generation server, storage, and accelerator connectivity. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Throughput: Multi-lane architecture supporting maximum theoretical link speeds.

Low Latency: Optimized datapath for minimal latency, crucial for coherent interconnects like CXL and UCIe.

Virtualization Support: Hardware support for SR-IOV to enable efficient resource sharing in virtualized environments.

Reliability features: Advanced RAS (Reliability, Availability, and Serviceability) features for enterprise class stability.

FEATURES
  • Compliant with PCI version 2.x Specification
  • Supports 32 bit address and data
  • Supports all types device select delays
  • Supports arbiter which is 100% PCI specification compliant
  • Supports all types of error detection
  • Provides parity on both data and address and allows implementation of robust client platforms.
  • Full multi-master capability allowing any PCI master peer-to-peer access to any PCI master/target.
  • Synchronous bus with operation up to 66 MHz
  • Forward and backward compatibility with PCI 66 MHz
  • Customization and integration service is available
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
  • Functional safety features (B: No certification, with safety features, in line with the development process).
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262 Available as Additional Feature at extra cost
  • Support additional functionality of RCB,PME,PTM,DMA,Atomic OP,CRS,TPH,Vendor specific Messages,Isochronous support
  • ISO26262 Functional Safety(ASIL B/D)
    • ISO26262 Safety Manual (SAM) Document
    • ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document
  • This core achieves ASIL-B and can be made to achieve ASIL-D as per ISO26262
  • Memories with ECC
  • Basic Firmware – Linux Driver
  • Customized SoC I/F
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the pci master slave IP. Ports of core module are the top level ports for the pci master slave IP.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesCore Clock FrequencyPipe Clock FrequencySystem Clock Frequency
TSMC 28nm46K66MHz66MHz33MHz
UMSC 55nm95K66MHz66MHz33MHz
SMIC 40nm53K66MHz66MHz33MHz

FPGA Device and FamilyLogic ResourcesCore Clock FrequencyPipe Clock FrequencySystem clock Frequency
AMD-xcvu9p-flga2104-2L-e7502 LUT's66MHz66MHz33MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.