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ETHERNET CYCLIC FEC IIP

IEEE 802.3 Standard Binary Cyclic Code

ETHERNET CYCLIC FEC IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET CYCLIC FEC IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Compliant with ETHERNET specification
  • Supports Full IEEE Standard 802.3.2022 Ethernet cyclic FEC functionality.
  • This FEC(Forward Error correction) methodology implements the (2112 , 2080) binary cyclic code is shortened from the cyclic Fire code (42987, 42955).
  • Supports FEC of 32 bits parity bits. This FEC can correct up to 11-bit burst error.
  • Supports the pipelined mechanism for the error correction.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Ethernet Cyclic FEC IP. Ports of core module are the top level ports for the Ethernet Cyclic FEC IP.

ENCODER: Encoder module is used to encode the input data and calculate the parity.

PARITY GENERATOR: It is used in encoder to calculate parity symbols.

STATE REGISTERS: State registers are used in encoder to store intermediate parity states while processing the data symbols sequentially.

PARITY MERGER: It merge the parity bytes into the ethernet stream.

DECODER: Decoder module is used to detect and correct the errors with the help of syndrome calculation.

SYNDROME LOGIC: Syndrome logic is used to calculate syndrome values from received FEC code word.

ERROR DETECTION: Error detection is used to detect the error.

SYNDROME EVALUATION: Syndrome evaluation is the decision and analysis stage to interprets the syndrome values.

ERROR CORRECTION: Error correction is used to correct the error.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyEncoder Clock FrequencyDecoder Clock Frequency
TSMC 28nm5.24k1GHz1GHz1GHz
SMIC 40nm50.34k1GHz1GHz1GHz
UMC 55nm80.82k1GHz1GHz1GHz

Logic ResourcesSystem Clock FrequencyEncoder Clock FrequencyDecoder Clock Frequency
873 LUT's1GHz1GHz1GHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.