AHB2APB BRIDGE IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech AHB2APB BRIDGE IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Forming the high-speed communication backbone of complex System-on-Chips. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Deadlock Free: Robust routing logic prevents system hang-ups under heavy load conditions.

Low Latency Bridging: Efficient clock domain crossing and protocol conversion with minimal cycle overhead.

High Frequency: Pipelined architecture designed to close timing at high clock frequencies in modern nodes.

Scalable: Easily configurable for simple bus fabrics or complex, multi-layer network-on-chip (NoC) implementations.

FEATURES

Compliant with AMBA AHB specification
Compliant with AMBA APB3 , AMBA APB4 specification
Translates AHB transactions into APB transactions
Endianness and data widths of both the interfaces are configurable
Data Phase timeout to send error response when there are no responses from APB
Accepts pipelining transfer of AHB
Supports single and fixed size incrementing bursts
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

FUNCTIONAL DESCRIPTION

CORE: Core module performs all the below functionalities in the AHB2APB BRIDGE IIP. Ports of core module are the top level ports for the AHB2APB BRIDGE IIP.

AHB SLAVE: AHB Slave is used to respond to a read or write operation within a given address-space range. It accepts address and control from the master and returns data/response.

APB MASTER: APB Master is use to initiate read and write operations by providing an address and control information.

DATA ALLIGNER: Data Aligner is used to adjust the data positions and size between AHB and APB formats.

AHB TRANSFER CONTROLLER: It controls and sequences incoming AHB read/write transactions inside the bridge.

APB TRANSFER CONTROLLER: It generates and controls APB protocol signals for each transfer.

ADDRESS DECODER: Address Decoder checks the APB address and identifies the corresponding AHB slave based on the configured address ranges.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 12nm	3.25K	100MHz
TSMC 28nm	2.06K	100MHz
TSMC 90nm	2.97K	100MHz
TSMC 130nm	2.97K	100MHz
TSMC 180nm	2.97K	100MHz
GF 180nm	2.47K	100MHz
SMIC 40nm	2.17K	100MHz
UMC 55nm	3.72K	100MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	343.33 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.