HDCP 1.x Transmitter IIP

High Bandwidth Digital Content Protection 1.x Transmitter IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech HDCP 1.x Transmitter IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Essential for safeguarding sensitive data in government, financial, and IoT applications. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Side-Channel Resistance: Design hardened against DPA (Differential Power Analysis) and other side-channel attacks.

High Performance: High-throughput encryption/decryption engines to match line-rate speeds of modern interfaces.

Standard Compliance: Fully compliant with NIST and ISO security standards.

Easy Integration: Standard system bus interfaces for straightforward integration into secure enclaves.

FEATURES

HDCP 1.x Transmitter IIP
Fully compliant with the HDCP version 1.4 specification and ensures standard-adherent operation across all supported configurations
Supports HDCP Transmitter functionality for Display Port, HDMI and MHL content interfaces.
Supports configurable cipher output widths of 8-bit, 16-bit, 24-bit or 32-bit.
Supports User loadable keys for the authentication process.
Integrates the standard SHA-1 algorithm for robust authentication.
Includes built-in HDCP Random number generator(RNG) functions.
Handles Encryption Status Signaling, including

Enhanced Encryption Status Signaling (EESS).
Original Encryption Status Signaling (OESS).

Processes System Renewability Message (SRM) and handles device revocation.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.

FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

AUTHENTICATION PROTOCOL: Implements the HDCP transmitter side authentication procedure to validate the downstream receiver's credentials and establish a secure session for protected content transmission.

SHA1: Executes SHA-1 hash during HDCP 1.x repeater authentication to generate V value, ensuring Key Selection Vector(KSV) list integrity during the second part of authentication.

KM CALC: Calculates the master key(Km) values required during the first part of authentication.

BLOCK CIPHER: Drives both part of authentication by generating pseudo-random outputs(from Km and An values)in the first part of authentication and producing the session key stream(Ro) in the second part of authentication

CIPHER GENERATOR: Generates the final cipher stream at configurable data widths of 8, 16, 24, 32.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System Clock Frequency	Cipher Clock Frequency
TSMC 28nm	51.07k	100Mhz	300Mhz
SMIC 40nm	54.38k	100Mhz	300Mhz
UMC 55nm	100.25k	100Mhz	300Mhz

FPGA Device and Family	Logic Resources	System Clock Frequency	Cipher Clock Frequency
Xilinx Vivado 2024.1 Virtex Ultrascale+ VCU118 xcvu9p-flga2104-2L-e	797 LUT's	100MHz	150MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.