ETHERNET 100BASET1 PCS IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 100BASET1 PCS IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Compliant with IEEE 802.3.2022 standard specifications Clause 96
Supports MII interface with 100Mbps speed
Supports 4b/3b Encoding and Decoding
Supports 33 bits side-stream Scrambler and Descrambler
Supports PAM3 encoding scheme
Supports 3B2T symbol mapper and demapper
Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
Supports loopback functionalities
Supports IEEE Standard 802.3.2022 Clause 98 Auto negotiation
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Ethernet 100baset1 PCS IP. Ports of core module are the top level ports for the Ethernet 100baset1 PCS 1G IP.

4B/3B Encoder: It convert the 4-bit input data into 3-bit code groups. The encoder groups incoming MAC data and maps inot the 3-bit symbols.

4B/3B Decoder: It takes incoming 3-bit code groups and convert into 4-bit.

Side-stream Scrambler: It is LFSR based scrambler that uses the 33 bit polynomial to generate the seed and produce the scrambled output data.

Side-stream descrambler: It uses the LFSR based descrambler that use the 33 bit polynomial to generate the seed and produce the descrambled output data.

PAM3 Encoding: It is 3 level Pulse Amplitude Modulation. It converts 3 ternary symbols into 3 voltage levels such as (-1,0,+1) for line signaling method.

CSR: CSR module has Control Status registers that controls the IP all the registers. The contents of the registers are decoded and assigned to its respective output port based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	MAC Clock Frequency	Serdes Clock Frequency
TSMC 28nm	40.76K	167MHz	125MHz	125MHz
UMSC 55nm	81.86K	167MHz	125MHz	125MHz
SMIC 40nm	43.86K	167MHz	125MHz	125MHz

FPGA Device and Family	Logic Resources	Clock Frequency	MAC Clock Frequency	Serdes Clock Frequency
Kintex 7,6793 LUT's	167MHz	125MHz	125MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.