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I2C Slave To AXI Bridge IIP

Inter-Integrated Circuit Slave To AXI Bridge IIP

I2C Slave To AXI Bridge IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech I2C Slave To AXI Bridge IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES
  • I2C v7.0 Slave To AXI Bridge.
  • Compliant with I2C version 7.0 specification.
  • Full I2C Slave Functionality.
  • Converts I2C Transactions into AXI write or read instructions.
  • Allows external devices to access the internal AXI Bus.
  • Useful for updating device software configuration from external device.
  • Useful for reading internal memory mapped registers and memory.
  • Supports Mailbox Read/Write functionality.
  • Supports Read/ Write access of external memory via AXI Master Interface.
  • Supports AMBA/Custom SOC Slave interface for software register configuration.
  • Supports monitoring of erroneous AXI transfers and reports error to the system.
  • Supports Start, Repeated start and Stop detection inbetween for all possible transfers.
  • Supports 7bit/10bit Addressing.
  • Supports following speed modes,
  • ->Standard mode.
  • ->Fast mode.
  • ->Fast plus mode.
  • ->High-speed mode.
  • Supports General call address handling.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module inter connects all the sub modules in I2C Slave AXI Bridge IIP(START, STOP, SDA OUT, SCL OUT, FSM, CSR). Ports of core module are the top level ports of Slave IP.

START: Start module detects the start condition on bus based on SDA and SCL line. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition.

STOP: Stop module detects the stop condition on bus based on SDA and SCL line. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

SDA OUT: SDA OUT module is to enable / disable SDA driver based on the signals from FSM.It is the block where value onto Slave’s SDA bus is loaded as per the value provided through the ports from FSM Module as I2C Write & Read Transfer (ACK/NACK Cycle) and I2C Read Transfer (Throughout the Read Data Frame).

FSM: FSM module process I2C commands once start is detected. FSM responds to I2C commands (ACK/NACK for Write & Read transfer and Read data for read transfer) only if Slave address is matched with the address driven on the I2C bus by the Master. The Slave FSM module includes the functionalities as Handling I2C write/read transactions.

CSR: CSR module holds control, status, interrupt, configuration registers for the I2C Slave to AXI Bridge IP which can be accessed via AMBA/Custom interface.

SCL OUT: SCL OUT module is used to stretch the clock, data will be driven and sampled based on this clock cycles.

SDA Buffer: SDA Buffer module is used to buffer for i_sda to separate clock and data path for i_sda.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 28nm18.39K100KHz
TSMC 12nm28.57K100KHZ
TSMC 90nm26.89K100KHZ
TSMC 130nm26.89K100KHZ
TSMC 180nm28.40K100KHZ
GF 180nm20.77K100KHZ
UMC 55nm32.07K100KHz
SMIC 40nm19.71K100KHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD Virtex Ultrascale +1619 LUT's100KHZ

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.