EtherCat Master IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Ethercat Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility andease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Compliant with EtherCAT Standard specification IEC61158
Compliant with IEEE Standard 802.3.2022 specification
Supports EtherCAT frame inside an Ethernet frame
Supports all types of EtherCAT data frames
Supports the standard TCP-IP and UDP-IP protocols
Supports Full software stack for EtherCAT
Supports Full duplex transmission
Supports Sync Manager and Mailbox
Supports Field Bus Memory Management Unit
Supports Error Detection using Ethernet’s Frame Check Sequence
Supports XGMII Interface
Supports conformance tests as per ETG.7000.2 V1.0.6 specification
Provides detailed statistics as per the specification
Supports MDIO (Clause 22 and Clause 45) Interface
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to Microprocessor/Microcontroller devices

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the EtherCAT Slave IP. Ports of core module are the top level ports for the EtherCAT Slave IP.

TX BLOCK: The transmit FSM receives the data drive into interface by encapsulating the Ethernet packet and frame headers.

RX BLOCK: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers. wraps process data into standard Ethernet frames.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	MAC Clock Frequency
TSMC 28nm	97.07K	312.5MHz	156.25MHz
UMSC 55nm	124.13K	312.5MHz	156.25MHz
SMIC 40nm	113.03K	312.5MHz	156.25MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	16137 LUT's	125MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.