The SivaKali Tech SVI3 Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with AMD_SVI3 specification as defined in version 1.01 Specification
Full SVI3 Slave Functionality.
Supports Multi-slave interface with explicit addressing
Supports as Terminal Slave, Non Terminal Slave and Ack Slave
Supports Daisy-chain Pipelining.
Supports Direct register read/write functionality
Supports Slave Enumeration and Addressing
Supports Multiple back to back to frames
Supports Telemetry stream operations
Supports all Global, Command Packets and Telemetry packets as per specification
Support Slave Acknowledgement frames
Supports Resynchronization
Supports SVC timeout function
Supports SVI3 Interface Enabling/Disabling
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the SVI3 Slave IP. Ports of core module are the top level ports for the SVI3 Slave IP
FSM: FSM module waits for a master frame,receives and decodes it,executes the command, and sends a formatted response with error handling befor returning to idle.This blocks implements all the features of AMD_SVI3 version 1.01 specification.
CSR: CSR module has all the Control registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
Protocol Clock
TSMC 28nm
7.32K
100MHz
10MHZ
UMSC 55nm
12.34K
100MHz
10MHZ
SMIC 40nm
8.54K
100MHz
10MHZ
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
20566 LUT's
29.762MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
