VIRTUAL GPIO IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech VIRTUAL GPIO IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES

Compliant with standard protocol of MIPI Virtual GPIO v0.9 specification
Bi-directional Virtual GPIO state information exchange
Transmission latency within the permissible limits
Wide range of clock frequency support (from sleep clock to higher frequency (78 MHz)
Dynamically switchable clock gears
GPIO Stream Length programmability
Ability to detect physical interface failure under corner case conditions, such as power failure, or a watchdog timer bite that renders the SoC unable to communicate via standard bus-based communication.
Minimum to no software required for driving the interface For lower transmission latency, a third wire providing clock is permitted, making it a 3-Wire VGI interface
Minimum impact on power and die area
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CSR: CSR module has the set of registers used to configure GPIO core, log the GPIO status, program the timeout value for Host and register to store the GPIO data.

CORE: Core module interconnects all the sub-modules in the Peripheral IP. Ports of core module are the top level ports for the Peripheral IP and the Core Module acts as the central interconnect hub.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	4.70K	100MHz
UMSC 55nm	8.71K	100MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	14516 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.