SWP Slave IIP

Single Wire Protocol Slave IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech SWP Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

Compliant with ETSI TS 102 613 and ETSI TS 102 221 Specification.
Complete SWP Uicc functionality.
Supports SWP Uicc test specification
ETSI TS 102 221 support
Supports SWP interface between CLF and UICC
Supports different types of layers,

Physical layer
Data link layer
MAC layer
LLC layer

Supports contacts activation and deactivation
Supports ACT LLC, SHDLC LLC and CLT LLC
Support SHDLC LLC frame types,

I-Frames
S-Frames
U-Frames

Supports configurable timing functions.

Acknowledge time
Guarding/transmit time
Connection time

Automatic handling of

Start of frame (SOF)
End of frame (EOF)
stuffing bits
CRC-16
calculation and generation in transmission
calculation and checking in reception

32-bit Transmit data register
32-bit Receive data register
CRC error, underrun, overrun flags
Frame reception and transmission complete flags
Slave resume detection flag
Exit from Stop 1 mode with a RESUME by slave event
Loopback mode for test purpose
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the SWP slave IP. Ports of core module are the top level ports for the SWP slave IP.

TFSM: TFSM module controls all transmit-side states including response framing,bit timing and end of frame handling.This blocks implements all the features of ETSI TS 102 613 and ETSI TS 102 221 specs.

RFSM: RFSM module controls all receive side states including serial data sampling, command validation and error handling.This blocks implements all the features of ETSI TS 102 613 and ETSI TS 102 221 specs.

CSR: CSR module has all the Control registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

P2S: P2S module converts parallel response data from the core into a serial SWP-compliant waveform for transmission.

S2P: S2P module converts incoming SWP serial bitstream into parallel command/data bytes for processing by the core.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	7.41K	40MHz
UMSC 55nm	13.36K	40MHz
SMIC 40nm	8.84K	40MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	22266 LUT's	40MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.