PSI5 Sensor IIP

• Conformance with PSI5 protocol specification V1.3 to V2.3
• Data rates of 125 kbit/s and 189 kbit/s supported
• Asynchronous and synchronous data transmission modes (control by microcontroller in synchronous mode)
• Supports Manchester encoder for upstream transmission
• Error recognition for transmission timing violations
• Configurable data word length 8, 10, 16, 20, 24 bit according to PSI5 standard
• Support of non PSI5 standard frame length 11... 33 bit
• Programmable response delay after sync pulse detection
• CRC check of received controller data implemented but CRC code transparent
• Support of Enhanced Serial Messages according to SENT SAE J2716 JAN 2010
• Supports 16-Bit time stamp (resolution: 1μs)
• Storage of up to 32 frames per channel with time stamp
• FIFO access and management
• Buffer overrun detection
• Buffer Memory Status Overview Registers
• Support of Sensor to ECU communication
• Generation of 3 or 6 bit CRC for data
• Start sequence and CRC generator for data
• One sum interrupt for general events
• Sticky interrupt flags, error interrupts optional (default disabled)
• Supports enabling and disabling of interrupts
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core module interconnects all the sub-modules in the PSI5 Sensor IP. Ports of core module are the top level ports for the PSI5 Sensor IP.

TFSM: Tfsm module implements the PSI5 transmit state machine for driving frame from Sensor to ECU. It performs the transactions on Sensor based on commands from CSR block.

RFSM: This module implements the PSI5 receiver state machine. In this module the RFSM samples the frame and stores the sampled frame. It samples the data, timestamp and CRC and stores.

RPRESCALER: RPrescaler module implements receiver prescaler. RPrescaler module is used to divide the PSI5 clock based on the given rprescaler value to derive the serial clock input for the reception of PSI5 Sensor.

TPRESCALER: TPrescaler module implements transmit prescaler. TPrescaler module is used to divide the PSI5 clock based on the given tprescaler value to derive the serial clock input for the transmission of PSI5 Sensor. By using the divied cloclk the TFSM drives the frame from Sensor to ECU.

ENCODER: ENCODER module implements the manchester encoder. In this module we are encoding and transmitting the encoded data to FSM.

TIMESTAMP: Timestamp module implements timestamp timer and clock divider. It is used to generate the clock by dividing the PSI5 clock based on the given Timestamp prescaler value and generates the timestamp data and external timestamp data.

J2176: J2716 module implements J2716 message bits processor for all slots. It will create the instance for each slot. It Implements the PSI5 receive J2726 message decoder.

J2176_SLOT: J2716_slot module implements J2716 message bits processor for given slot. It Implements the PSI5 receive J2726 message decoder for sampling the Enhanced Serial Message according to SENT SAE J2716 JAM 2010. It ensures the implementation of the SENT protocol within a PSI5 Sensor

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.