SDIO UHS-II Analog PHY IP

Secure Digital Input Output-Ultra High Speed Phase II Analog PHY IP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech SDIO UHS-II Analog PHY IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. High-performance analog front-ends engineered for the most demanding high-speed connectivity standards. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Broad Foundry Support: Silicon-proven and optimized for leading foundries including TSMC, SMIC, UMC, and GlobalFoundries.

Precision Timing Architecture: Advanced DLL-based clocking for reliable data capture and phase alignment in high-speed storage.

Functional Safety Ready: Developed with ISO 26262 standards in mind, providing the reliability required for automotive and industrial missions.

Ultra-Low Power & Area: Industry-leading PPA (Power, Performance, Area) metrics achieved through meticulous circuit design and layout.

FEATURES

Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II
Specification Volume 1: System and Protocol”.
Per lane data rate between 390Mb/s to 1.56Gb/s.
Supports peak interface speed of 3.12Gb/s (Half-duplex); 1.56Gb/s in Full-duplex mode.
Sub-LVDS Differential PHY signaling.
Low frequency differential reference clock (1/15 or 1/30) of data rate.
Supports Spread Spectrum clocking to reduce EMI.
Flexible transmission rates from 390Mb/s – 1.56Gb/s (each lane).
Multiple power saving modes: Dormant, Line standby.
Low power, reduced EMI operation.
Integrated solution with built-in termination, no external components required.
Easily ported to various process nodes and foundries.

FUNCTIONAL DESCRIPTION

ASIC AND FPGA IMPLEMENTATION

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

GDSII Layout (Hard Macro).
LEF Abstract for Place & Route.
CDL Netlist for LVS and Simulation.
LIB (.lib) Timing, Power, and Noise Models.
Verilog Behavioral/Functional Models.
Integration Guide and Application Notes.
Characterization and Simulation Reports.
LVS, DRC, and ERC Verification Reports.
ISO 26262 Safety Manual (SAM) and FMEDA (for Automotive).