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SMPTE-SDI Transmitter IIP

Society of Motion Picture and Television Engineers Serial Digital Interface Transmitter IIP

SMPTE-SDI Transmitter IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech SMPTE-SDI Transmitter IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Fully compliant with the following specification and ensures standard-adherent operation across all supported configurations:
    • SD: st0259-2008.
    • HD: st0292-1-2011 and st0372-2011.
    • 3G: st0425-1-2011, st0425-3-2015 and st0425-5-2015 .
    • 6G: st2081-10-2015, st2081-11-2016 and st2081-12-2016.
    • 12G: st2082-10-2015, st2082-11-2016 and st2082-12-2016.
  • Dynamically supports link configurations of 1, 2 and 4 links.
  • Supports link rates up to 12Gbps.
  • Supports configurable input pixel processing of 1, 2, 4 and 8 Pixels Per Clock (PPC).
  • Supports programmable parallel interface widths of 10bits, 20bits, 40bits and 80bits.
  • Supports maximum resolution up to 8k@60Hz.
  • Compatible with the video formats which are mentioned in SMPTE-SDI specification:
    • RGB 4:4:4 (30 Bits Per Pixel)
    • RGB 4:4:4 (36 Bits Per Pixel)
    • RGBA 4:4:4:4 (40 Bits Per Pixel)
    • YCbCr 4:2:2 (16 Bits Per Pixel)
    • YCbCr 4:4:4 (30 Bits Per Pixel)
    • YCbCr 4:2:2 (20 Bits Per Pixel)
    • YCbCr 4:2:0 (20 Bits Per Pixel)
    • YCbCr 4:4:4 (36 Bits Per Pixel)
    • YCbCr 4:2:2 (24 Bits Per Pixel)
    • YCbCr 4:2:0 (24 Bits Per Pixel)
    • YCbCrA 4:2:2:4 (36 Bits Per Pixel)
    • YCbCrA 4:4:4:4 (40 Bits Per Pixel)
  • Supports 2 to 512 audio channels.
  • Compatible with sample rates up to 96KHz.
  • Performs the Scrambled NRZI channel encoding.
  • Compatible with ECC-based audio data protection.
  • Supports Cyclic Redundancy Check (CRC).
  • Supports Error Detection and Handling (EDH) for SD mode only.
  • Supports Sync-Bit insertion for 6G and 12G standards.
  • Compatible with Ancillary data packets:
    • Audio Data
    • Audio Control Data
    • Time and Control Data
    • Payload Identifier
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

VIDEO SPLITTER: Splits the incoming video data into respective sub-images based on the active SDI mode, link configuration and mapping structure.

VIDEO CONTROL GEN: Generates essential video control information, including pixel and line status, field indication and Timing Reference Signal (TRS) Pattern insert positions.

VIDEO PACKER: Packs the input video data and control information according to the selected SDI mode, link configuration, mapping structure and color format.

AUDIO SAMPLER: Samples the incoming audio data and packs the respective streams based on the SDI mode, link configuration and mapping structure.

FRAMER: Insert TRS patterns based on the generated control information and embeds ancillary data packets into the available blanking spaces as defined by the SMPTE specification.

LINK: Rearranges the stream data based on the SDI mode, performs NRZI channel encoding and generates the final output stream formatted for the selected SDI standard.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyLink Clock frequencySerdes Clock Frequency
TSMC 28nm15.48K100MHz74.25MHz74.25MHz74.25MHz
SMIC 40nm16.32K100MHz74.25MHz74.25MHz74.25MHz
UMC 55nm29.36K100MHz74.25MHz74.25MHz74.25MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyLink Clock frequencySerdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e2720 LUT's100MHz74.25MHz74.25MHz74.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.