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Automotive LIN Analog PHY IP

Robust and Ultra-Low Power Local Interconnect

Automotive LIN Analog PHY IP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Automotive LIN Analog PHY IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. High-performance analog front-ends engineered for the most demanding high-speed connectivity standards. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Broad Foundry Support: Silicon-proven and optimized for leading foundries including TSMC, SMIC, UMC, and GlobalFoundries.

Exceptional Noise Immunity: Specialized analog front-end design for superior performance in harsh industrial and automotive environments.

Functional Safety Ready: Developed with ISO 26262 standards in mind, providing the reliability required for automotive and industrial missions.

Ultra-Low Power & Area: Industry-leading PPA (Power, Performance, Area) metrics achieved through meticulous circuit design and layout.

FEATURES
  • Fully compliant with LIN 2.0, 2.1, 2.2, 2.2A, and ISO 17987-4:2016 standards.
  • Supports standard data rates up to 20 kbps and high-speed Flash programming mode (100 kbps).
  • Broad supply voltage support (4V to 40V) for compatibility with 12V and 24V board nets.
  • Optimized electromagnetic emission (EME) via integrated slope control and wave-shaping.
  • Superior bus protection: ±60V DC tolerance on LIN bus and high ESD immunity (15kV IEC 61000-4-2).
  • Ultra-low power Sleep mode (<10µA) with reliable remote wake-up recognition.
  • Advanced fail-safe logic: TXD dominant timeout, thermal shutdown, and battery/ground loss protection.
  • AEC-Q100 Grade 0 qualified for mission-critical automotive reliability (-40°C to +150°C).
  • Integrated Master/Slave termination resistors and diodes to minimize external component count.
LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • GDSII Layout (Hard Macro).
  • LEF Abstract for Place & Route.
  • CDL Netlist for LVS and Simulation.
  • LIB (.lib) Timing, Power, and Noise Models.
  • Verilog Behavioral/Functional Models.
  • Integration Guide and Application Notes.
  • Characterization and Simulation Reports.
  • LVS, DRC, and ERC Verification Reports.
  • ISO 26262 Safety Manual (SAM) and FMEDA (for Automotive).