CORE: Core module interconnects all the sub-modules in ETHERNET 10G KR PCS IP. Ports of core module are the top level ports for the ETHERNET 10G KR PCS IP.
TX FSM: It performs the 64B/66B encoding and scrambled data to transmit.
FEC TRANSMITTER: The FEC transmitter constructs the FEC block of 2080 bits and perform the transcoding, and than scrambling FEC encoded data.
FEC ENCODER: This block performs FEC encoding on the transcoded data and adds the FEC parity at the end of the each FEC block which provides 2112 bit FEC block.
GEARBOX TX FIFO: This FIFO module stores Tx data and process the data with the different read and write clock domain based on the PMA width.
GEARBOX TX: The Tx gearbox module is a digital logic block used to adapt data between two different bus widths and clock frequencies based on the PMA width.
GEARBOX RX: The receive gearbox module is used to adapt the data between two different bus widths and clock frequencies, based on the PMA width.
GEARBOX RX FIFO: This FIFO module stores Rx data and process the data with the different read and write clock domain based on the PMA width.
FEC RECEIVER: The FEC receiver implements the FEC lock FSM and descrambling the FEC data and checks the FEC parity and performs the detranscoding.
FEC DECODER: This block process to check the FEC parity and decode the FEC descrambling data.
BLOCK SYNC: The block synchronizer is used to detect the valid 66bits of data block.
BER: The BER monitor continuously monitors the input data and validates whether it receives a valid sync header.
RX FSM: The RX FSM process the descrambling and 64B/66B decoding of the 66bit valid input data.
AN ARBITER: This block is implemented to AN state transistion to the final resolution, which will be process the information between the DME TX and DME RX to provides the AN process.
AN DME TX: This block handles the transmitter DME pages after that encodes the AN DME page.
AN DME RX: This block after DME page decoding handles the reception of AN DME page.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
