LPC Host IIP

low-pin-count Bus Interface Host IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech LPC Host IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

Compliant with version 1.1 LPC Specifications
Full LPC Host functionality
Supports the following operations

Memory read and write
I/O read and write
DMA read and write
Bus Master memory read and write
Bus Master I/O read and write
Firmware memory read and write

Supports all transfer sizes
Supports 128 Bytes for Firmware read
Supports variable number of wait-states
Supports Sync timeout detection and abort transfer
Supports Sync field based error detection and reporting
Supports wake-up and other power state transitions
Supports both typical timing and extended timing for LFRAME#
Host is capable of generating all types of LPC transactions
Support up to 32 SERRIRQ IRQ/Data frames
Supports Abort Mechanism as per specification
Supports soft reset
Supports Reset policy
Supports LPME#, LPCPD#, CLKRUN# Power management signals
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the LPC Host IP. Ports of core module are the top level ports for the Host IP. LCLK clock is derived from i_clk based on prescaler value.

PRESCALER: Prescaler module is used to derive the Serial LPC clock from the system clock based on the programmed clock divider value.

FSM: FSM module generates the LPC Host transactions on Host based on Start opcodes from CSR block. This blocks implements all the features from LPC Host specs.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

LDRQ: This module controls the LDRQ# lines to handle the DMA channel and Bus Mastering,which will be requested from LPC devices. LDRQ# is synchronous with LCLK

SERIRQ: This module controls to drive and sample the SERIRQ# signal to indicate LPC Interrupts to software. SERIRQ# is synchronous with LCLK

LDRQ LEAF: This module FSM controls the Information of LDRQ lines to get which request is asserted from device either DMA request or Bus-Master Request.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System Clock Frequency	Protocol Clock Frequency
TSMC 28nm	7.99K	100MHz	33MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	13317 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.