CoE IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech CoE IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

Supports the MAC service provided by the IEEE 802.3-2022 standard specification
Supports accessing the internal registers of the IP's for configuration and status reports
Supports CoE frame encapsulation in the Ethernet frame payload field
Supports MII,GMII,XGMII,RGMII,RMII interfaces
Supports the below commands through the CoE frame, Write command Read command Write command Ack/Response Read command Error Error command response
Supports the following fields in the CoE frame payload, Version(8 bits) – Version number of the CoE protocol Sequence number of command(8 bits) – Sequence number of CoE frame SoC write address(32 bits) – It is used for write the data in particular soc
address Length (8 bits) – Denotes the number of data bytes for transmission and
reception functions Data - 8 * Len (Write data) – This data is written in the particular register.
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the CoE IP. Ports of core module are the top level ports for the CoE IP.

DECODER: DECODER module implements COE decoding of ethernet frame and extract payload and Source Address/Destination Address by driving the RX MAC signals and push them into FIFO

LFIFO: LFIFO stores the length of the data.

DFIFO: DFIFO stores the data.

RFSM: Receive FSM module receives the frame and samples with command, sequence number, address bits and error to write into Configurable Registers.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

TFSM: Transmit FSM module samples the data from the Configurable register and push them into FIFO.

ENCODER: Encoder module implements framing of ethernet frame, inserts length field and drives the TX MAC signals.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	10.5K	50MHz
UMSC 55nm	12.1K	50MHz
SMIC 40nm	9.7K	50MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	175 LUT's	50MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.