The SivaKali Tech JESD204D Receiver IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with JESD204 specification JESD204D version
Full JESD204D receive functionality
Supports 1 to 8 number of lanes
Supports 1 to 64 number of converters per receiver
Supports 1 to 8 number of samples per converter
Supports frame sizes of 1, 2, 4, 8 and 16 octets per frame
Supports HD-mode
Supports 1 to 32 bit data width per converter
Supports CF = 0 and 1 control words per frame clock period per link
Supports 0 to 3 control bits per sample
Supports 4, 8, 12, 16, 20, 24, 28 and 32 bits per sample
Supports different Serdes interfaces 10, 20, 40, 60 bits and custom bits per lane
