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HDMI Sink v2.1 IIP

High Definition Multimedia Interface Sink v2.1 IIP

HDMI Sink v2.1 IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech HDMI Sink v2.1 IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Delivering premium visual experiences for digital signage, broadcast, and consumer displays. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Quality Compression: Visually lossless compression algorithms optimized for minimal silicon area.

Real-Time Performance: Ultra-low latency processing suitable for live streaming and interactive applications.

Multi-Standard Support: Configurable to support various resolutions, frame rates, and color formats.

Power Efficient: Architecture optimized to minimize power consumption for portable multimedia devices.

FEATURES
  • HDMI Sink v2.1
  • Fully Compliant with HDMI specification v2.1b specification and ensures standard-adherent operation across all supported configurations.
  • Backward compatible with HDMIv2.0 and HDMIv1.4.
  • Supports TMDS Character link rates from 340 Mcsc to 600 Mcsc.
  • Supports FRL Lane link rates of 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps.
  • Supports configurable output pixel processing of 1, 2, 4 and 8 pixels per clock
  • Supports programmable parallel interface widths of 10bits, 20bits, 40bits and 80bits.
  • Supports maximum uncompressed video resolutions upto 10k@60Hz.
  • Supports maximum compressed video resolutions upto 10k@120Hz.
  • Compatible with the video formats which are mentioned in HDMIv2.1b,
    • RGB 4:4:4 (24,30,36,48 Bits Per Pixel)
    • YCbCr 4:4:4 (24,30,36,48 Bits Per Pixel)
    • YCbCr 4:2:2 (24 Bits Per Pixel)
    • YCbCr 4:2:0 (24,30,36,48 Bits Per Pixel)
  • Compatible upto 32 audio channels.
  • Compatible with audio sample rates from 32 KHz to 1.536 MHz.
  • Compatible with standard and compressed audio formats including,
    • Audio Sample (LPCM and IEC 61937 compressed formats)
    • ACP packet, One bit audio sample packet, and DST audio packet
    • High Bitrate (HBR) Audio Stream Packet (IEC 61937)
    • Audio InfoFrame, Audio Metadata Packet, and Extended Metadata Packet
    • 3D Audio Sample Packet (LPCM format only) and One Bit 3D Audio Sample Packet
    • Multi-Stream Audio Sample Packet, and One Bit Multi-Stream Audio Sample Packet
    • Dynamic Range and Mastering InfoFrame
  • Supports all secondary video data packet formats including,
    • Null packet
    • General Control packet
    • ISRC packet
    • Gamut Metadata Packet
    • Vendor-Specific InfoFrame
    • AVI InfoFrame
    • Audio clock regeneration
  • Performs 18b/16b Decoding for FRL mode and 10b/8b Decoding for TMDS channel.
  • Performs descrambler fully complaint with the HDMI 2.1b specification.
  • Supports Error Correction Codes (ECC) to perform error correction in dataisland packets.
  • Compatible with Forward Error Correction (FEC).
  • Compatible with High-bandwidth Digital Content Protection System (HDCP) 2.2/2.3.
  • Compatible with Audio Return Channel (ARC) and Enhanced Audio Return Channel (eARC).
  • Compatible with Consumer Electronics Control (CEC 2.0).
  • Compatible with Display Data Channel (DDC).
  • Compatible with Video Transport VESA Display Stream Compression (DSC) 1.2a.
  • Compatible with legacy DVI and Dual-Link DVI Standards.
  • Compatible Variable Refresh Rate (VRR), Fast Vactive (FVA) and Auto low Latency mode (ALLM).
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

TMDS LOGICAL PHY: Synchronizes the TMDS data steam, detects preambles, decodes video and control/data-island symbols, and performs descrambling.

GEARBOX: Converts the received 10bit, 20bit, 40 bit or 80 bit serdes data into constant 80 bit internal data width.

DESKEW: Compensates for inter-lane timing differences across HDMI data channels.

FRL LOGICAL PHY: Performs 18b to 10b decoding, RS-FEC(Reed-Solomon Forward Error Correction and data de scrambling on received FRL stream.

FRL LINK TRAINING FSM: Manages the FRL Link Initialization by handling link rate selection, lane configuration and training sequences to establish a successful link.

TMDS LINK LAYER: Unpacks the decoded data as per HDMI specification and provides formatted video, audio, control information as output.

VIDEO UNPACKER: Converts the incoming HDMI video packets into a continuous pixel stream and provides video timing signals as output.

DI UNPACKER: Unpacks the decoded data-island packet and delivers the audio samples and auxiliary control information.

HPD: Monitors and processes Hot Plug Detect (HPD), handles plug, unplug and interrupts events to trigger link initialization and EDID reads.

I2C SLAVE: Implements I2C transactions to communicate with source device, enabling EDID and SCDC access for display capability, link configuration and status monitoring.

EARC TX: Implemented optionally to transmits high bandwidth, high quality audio from HDMI sink to external audio devices

CEC: Implemented optionally to enable device to device control and coordination over the HDMI CEC bus allowing seamless command exchange between connected HDMI devices.

HDCP: Implemented optionally to authenticate the HDMI source and securely decrypts protected audio-video content, ensuring compliance with HDCP content protection requirements.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyTMDS Clock FrequencyFRL Clock FrequencySerdes Clock Frequency
TSMC 28nm88K100MHz74.25MHz75MHz150MHz150MHz
SMIC 40nm94K100MHz74.25MHz75MHz150MHz150MHz
UMC 55nm167K100MHz74.25MHz75MHz150MHz150MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyTMDS Clock FrequencyFRL Clock FrequencySerdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e27833 LUT's100MHz74.25MHz75MHz150MHz150MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.