SBWP Master IIP

• Compliant with version 2.0 Safe-by-Wire Plus Specifications
• Full SBWP Master functionality
• Supports occupant restraints bus for deployable devices and for sensors
• Deployment bus for squibs and optionally for static occupancy sensors
• sensor bus for smart or simple impact sensors, dynamic occupancy sensors and optionally for static occupancy sensors
• combined sensor / deployment bus
• Supports Bi-directional two-wire bus with integrated power distribution
• Master-Slave operation
• Babbling-idiot protection for deploy messages from master
• Provides optional interrupt possibilities for smart impact sensors
• Optional multi-master operation
• Supports variable bus speed with self-clocking slaves
• 20 kbps, 40 kbps, 80 kbps or 160 kbps +/- 13%
• Data throughput example: at 160 kbps, (=160 kHz): * Transfer time of a deploy message controlling up to 12 deployable devices < 200 μs * Transfer time for retrieving 8-bit data from 3 impact sensors < 250 μs
• Supports, but does not require, speed change for high-speed deployment messages, initiated by the master
• Supports, but does not require, speed change for high-speed sensor polling messages, initiated by sensors ("interrupt" from sensor)
• Supports flexible bus topologies: bus, tree, ring, mixed
• Allows design of daisy chain systems, parallel systems and mixed systems
• Bus length of parallel systems up to 40 m
• Bus length of daisy-chain systems up to 25 m
• Supports real-time recovery from single-point bus shorts to any voltage within specified range
• Supports communication error detection by transmitter (data read-back) and by receiver (CRC)
• Supports multi-level protection against inadvertent deployment
• Detection of bit errors by master and by slave
• Special bus level reserved for deploy messages ("analog safing")
• Deployment only possible after charging of the energy reserve capacitor (ERC) in the deployable device
• Deployment only possible when deploy-enable message has been sent before
• Supports the use of two deploy switches, which can be controlled and diagnosed independently over the bus
• Allows the use of small hold-up capacitors in the slaves
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core module interconnects all the sub-modules in the SWBP Master IP. Ports of core module are the top level ports for the SWBP Master IP.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

FSM: FSM module implements the data transmission and reception functionality

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.