I2C Slave IIP

Inter-Integrated Circuit Slave IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech I2C Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES

I2C v7.0 Slave.
Compliant with I2C version 7.0 specification.
Full I2C Slave Functionality.
Supports Start, Repeated start and Stop detection inbetween for all possible transfers.
Supports 7bit/10bit Addressing.
Supports following speed modes,
->Standard mode.
->Fast mode.
->Fast plus mode.
->High-speed mode.
Supports General call address handling.
Supports clock stretching.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the I2C Slave IIP. Ports of core module are the top level ports for the I2C Slave IIP.

START: Start module detects the start condition on I2C bus. Start detect from this module triggers Slave FSM, to process a I2C transaction.

FSM: FSM module process I2C commands once start is detected. FSM responds to I2C commands (ACK/NACK for Write & Read transfer and Read data for read transfer) only if Slave address is matched with the address driven on the I2C bus by the Master.

SDA OUT: SDA OUT module is to enable / disable SDA driver based on the signals from FSM.It is the block where value onto Slave’s SDA bus is loaded as per the value provided through the ports from FSM Module as I2C Write & Read Transfer (ACK/NACK Cycle) and I2C Read Transfer (Throughout the Read Data Frame).

CSR: CSR module holds control, status, interrupt, configuration registers for the I2C Slave IP which can be accessed via AMBA/Custom interface.

STOP: Stop module detects the stop condition on bus based on SDA and SCL line. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	6.99K	100KHZ
TSMC 12nm	10.15K	100KHZ
TSMC 90nm	10.01K	100KHZ
TSMC 130nm	10.01K	100KHZ
TSMC 180nm	10.47K	100KHZ
GF 180nm	7.35K	100KHZ
SMIC 40nm	7.39K	100KHZ
UMC 55nm	12.40K	100KHZ

FPGA Device and Family	Logic Resources	Clock Frequency
AMD Virtex Ultrascale +	393 LUT's	100KHZ

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.