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SMPTE-SDI Receiver IIP

Society of Motion Picture and Television Engineers Serial Digital Interface Receiver IIP

SMPTE-SDI Receiver IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech SMPTE-SDI Receiver IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Fully compliant with the following specification and ensures standard-adherent operation across all supported configurations:
    • SD: st0259-2008.
    • HD: st0292-1-2011 and st0372-2011.
    • 3G: st0425-1-2011, st0425-3-2015 and st0425-5-2015 .
    • 6G: st2081-10-2015, st2081-11-2016 and st2081-12-2016.
    • 12G: st2082-10-2015, st2082-11-2016 and st2082-12-2016.
  • Dynamically supports link configurations of 1, 2 and 4 links.
  • Supports link rates up to 12Gbps.
  • Supports configurable output pixel processing of 1, 2, 4 and 8 Pixels Per Clock (PPC).
  • Supports programmable parallel interface widths of 10bits, 20bits, 40bits and 80bits.
  • Supports maximum resolution up to 8k@60Hz.
  • Compatible with the video formats which are mentioned in SMPTE-SDI specification:
    • RGB 4:4:4 (30 Bits Per Pixel)
    • RGB 4:4:4 (36 Bits Per Pixel)
    • RGBA 4:4:4:4 (40 Bits Per Pixel)
    • YCbCr 4:2:2 (16 Bits Per Pixel)
    • YCbCr 4:4:4 (30 Bits Per Pixel)
    • YCbCr 4:2:2 (20 Bits Per Pixel)
    • YCbCr 4:2:0 (20 Bits Per Pixel)
    • YCbCr 4:4:4 (36 Bits Per Pixel)
    • YCbCr 4:2:2 (24 Bits Per Pixel)
    • YCbCr 4:2:0 (24 Bits Per Pixel)
    • YCbCrA 4:2:2:4 (36 Bits Per Pixel)
    • YCbCrA 4:4:4:4 (40 Bits Per Pixel)
  • Supports 2 to 512 audio channels.
  • Compatible with sample rates up to 96KHz.
  • Performs the NRZI channel decoder and data descramber.
  • Compatible with ECC based audio data protection recovery/correction.
  • Supports Cyclic Redundancy Check (CRC) verification.
  • Supports Error Detection and Handling (EDH) extraction/checking for SD mode only.
  • Supports Sync-Bit detection for 6G and 12G standards.
  • Compatible with Ancillary data packets:
    • Audio Data
    • Audio Control Data
    • Time and Control Data
    • Payload Identifier
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

LINK: Performs NRZI channel decoding, locks onto the incoming link data, removes skew between the links and de-merges the stream data based on the active SDI mode.

DEFRAMER: Monitors the Timing Reference Signal (TRS) and Ancillary (ANC) patterns, removes the framing overhead and separates the active video and embedded ancillary data packets.

VIDEO UNPACKER: Unpacks the video information based on the SDI mode, link configuration, mapping structure and color format. It also reconstructs the video data and essential control information (such as link, pixel and field status)

VIDEO GEN: Reconstructs the final video output based on the extracted video data and control signals and system video parameters.

ANCILLARY UNPACKER: Identifies received ANC packets, splits them by type and routes them to dedicated downstream interfaces (such as Audio, Payload ID and Time and Control data).

AUDIO GEN: Reconstructs synchronized audio data streams based on the incoming audio control and data packet information.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyLink Clock frequencySerdes Clock Frequency
TSMC 28nm18.576K100MHz74.25MHz74.25MHz74.25MHz
SMIC 40nm19.58K100MHz74.25MHz74.25MHz74.25MHz
UMC 55nm35.23K100MHz74.25MHz74.25MHz74.25MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyLink Clock frequencySerdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e3623 LUT's100MHz74.25MHz74.25MHz74.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.