TIMER IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech TIMER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES

Supports 32 timers each of 32 bit
Supports up/down counting modes
Supports configurable counter width
Supports to count a maximum value of 32'hFFFFFFFF in Generate and Capture mode
Supports to count a maximum value of 64'hFFFFFFFFFFFFFFFF in Cascade mode
Supports to generate a pulse after an interval
Supports to generate a square waveform
Supports to capture a value on trigger event
Supports automatically reloading value
Supports to hold count value
Supports PWM mode
Supports halting and resuming timer
Supports cascaded mode of operation
Supports enabling and disabling of interrupts
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CSR: CSR module has all the control and status registers. It contains prescaler register to store the prescaler value, timeout register to store timeout value and instances of Regs block which contains individual Timer registers.

PRESCALER: Prescaler module is used to generate a clock enable output to Timer to count for number of clock cycles. It is used to extend the range of Timers.

REGS: Regs Module has the load register, count register and control register for each Timer individually.

TIMER: Timer block gets the decoded Timer configuration inputs from Regs block. It receives the mode, enable, output enable, trigger enable, load signal, arht signal and udt signal from Regs block. Timer block sends the PWM enable, gen_out, count inputs to the PWM block.

PWM: PWM Module receives pwm enable signals from two consecutive Timers.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System Clock Frequency
TSMC 12nm	4.88K	100MHz
TSMC 28nm	3.12K	100MHz
TSMC 90nm	4.47K	100MHz
TSMC 130nm	4.47K	100MHz
TSMC 180nm	4.65K	100MHz
UMC 55nm	5.64K	100MHz
SMIC 40nm	3.31K	100MHz
GF 180nm	3.37K	100MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	51685 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.