CORE: Core module interconnects all the sub-modules in the CPRI IP. Ports of core module are the top level ports for the CPRI IP.
GMII_RECEIVER: GMII_RECEIVER(Gigabit Media Independent Interface) module implements The receive FSM receives the data (frame octets) from underlying physical layer and sends them to CPRI
HDLC_RECEIVER: HDLC_RECEIVER(High-Level Data Link Control) Receives the 8 bit input data from hdlc_rxd. The hdlc_rx_dv signal indicates the received input valid data. The error hdlc_rx_er signal indicates the error data is received. The FSM check the flag opening value and received the start of frame signal. The FSM do bit stuffing method for hdlc data stream
AXC_CTRL_PACK: AXC_CTRL_PACK module implements the AXC CTRL pack
VSS_PACK: VSS_PACK(Vendor Specific Sub Channel) module includes The VSS packs the 32 bit input data into 64 bit data based on byte enable, Once the data is packed it pushed into Transmit VSS async FIFO.
RTVS_PACK: RTVS_PACK(Real time vendor specific) module implements the RTVS pack RTVS_PACK module implements the data request available only for CPRI higher bit rate.The RTVS packs the 32 bit input data into 64 bit output data based on byte enable, Once the data is packed it pushed into Transmit RTVS async FIFO
AxC_MAP: AxC(Antena Carrier) module includes mapping mode is followed by CSR configuration register value,The AxC data pack with respect to 4,5,6,7,8,9,10,11,12,15,16,20 samble bit rate, If map method is 0, it receives the 128 bit data from axc_tx_stream{0-31} and pushed into transmit AXC async FIFO
TX_PRBS: TX_PRBS(Physical Coding Sublayer) module implements the Tx PRBS
RX_PRBS: RX_PRBS(Physical Coding Sublayer) module implements the Rx PRBS
SYNC_FSM:
The sync FSM received the FIFO data and checks the comma character and enables the synchronization:
TX_FSM: TX_FSM module implements CPRI TX
ENCODER_8B10B: ENCODER_8B10B module implements the transmitter 8b/10b encoder
DECODER_10B8B: DECODER_10B8B module implements the receiver 10b/8b decoder
TX_PCS: TX_PCS module implemets the CPRI TX pcs
AM_FSM: AM_FSM(Alignment fsm) module implements the AM Insertion
257B_TO_160b_CONVERTER: 257B_TO_160b_CONVERTER module Implements the 257 to 160 bit converter
FEC_ENCODER: FEC_ENCODER(Forward Error Correction) implemets the Fec encoding
FEC_ENCODER_40BIT_MODE: FEC_ENCODER_40BIT_MODE implemets the Fec Encoder 40bit mode
FEC_DECODER_40BIT_MODE: FEC_DECODER_40BIT_MODE implemets the fec Decoder 40bit mode
AM_LOCK_FSM: AM_LOCK_FSM(Alignment lock fsm) implemets the AM lock state meachine
160B_TO_257B_CONVERTER: 160B_TO_257B_CONVERTER module Implements the 160 to 257 bit converter
FEC_DECODER: FEC_DECODER module Implements the clause 119 RS FEC
AM_REMOVAL_FSM: AM_REMOVAL_FSM module Implements the CLAUSE 119 PCS Layer AM REMOVAL FSM
TX_GEARBOX: TX_GEARBOX module implements transmit path gearbox for serdes width 8,10,16,20,32,40,64 bit
RX_FSM: RX_FSM module implements CPRI RX
RX_PCS: RX_PCS module implements CPRI RX pcs
RX_GEARBOX: RX_GEARBOX module implements transmit path gearbox for serdes width 8,10,16,20,32,40,64 bit
GMII_TRANSMITTER: GMII_TRANSMITTER(Gigabit Media Independent Interface) module implements the GMII transmitter
HDLC_TRANSMITTER: HDLC_TRANSMITTER(High-Level Data Link Control) module implements the HDLC transmitter
AXC_CTRL_UNPACK: AxC_CTRL_UNPACK module implements the CTRL AXC unpack
VSS_UNPACK: VSS UNPACK module implements the VSS unpack
RTVS_UNPACk: RTVS_UNPACK module implements the RTVS unpack
AXC_DEMAP: AxC_DEMAP module implements the AXC demap
CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.
