The SivaKali Tech PMBUS Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with I2C version 7.0 Specification
Compliant with SMBus version 3.3.1 Specification
Compliant with version 1.5 of PMBus Bus Specification
Supports HCI and Non HCI Interface
Full I2C, SMBus and PMBus Master Functionality
Supports Start, repeated start and stop for all possible transfers
Supports 7bit/ 10bit Addressing
Standard-mode (Sm): up to 100 kbit/s, bidirectional
Fast-mode (Fm): up to 400 kbit/s, bidirectional
Fast-mode Plus (Fm+): up to 1 Mbit/s, bidirectional
High-speed mode (Hs-mode): up to 3.4 Mbit/s, bidirectional
Ultra Fast-mode (UFm): up to 5 Mbit/s, unidirectional
Supports I2C Write/Read command
Supports all the commands as per Specification
--> Quick command
--> Send byte command
--> Receive byte command
--> Write byte command
--> Write word command
--> Read byte command
--> Read word command
--> Block write command
--> Block read command
--> Block write and read process call command
--> Write 32 command
--> Read 32 command
--> Write 64 command
--> Read 64 command
Supports Zone write and Zone read
Supports Extended command protocol
Supports General call address
Supports Sending command to a group
Supports Address Resolution Protocol
Supports Device fault management
Supports Packet Error checking
Supports alert and suspend handling
Supports Master arbitration and Clock synchronization
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION
CORE: Core module inter connects all the sub modules in PMBus Master (CSR, prescaler, MFSM). Ports of core module are the top level ports of Controller IP.
PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock (SCL) input for I3C.
MASTER FSM: Master FSM module process the commands once pending request from CSR and host controller bus is enabled.For write transfer master FSM will send slave address, R/W bit,Write data and waits for ACK/NACK from slave.
CSR: CSR module has all the configuration registers of Master, Slave and Interrupt status registers and Sync FIFO implementation for write and read operation.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 28nm
2.73K
25MHz
UMSC 55nm
4.95K
25MHz
SMIC 40nm
3.02K
25MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD virtula ultrascale
51685 LUT's
25MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
