MIPI UniPro IIP

• MIPI UniPro v3.0
• Supports MIPI UNIPRO specification version 1.6,1.8,2.0 and 3.0
• Supports MIPI M-PHY specification 3.0,4.1,5.0 and 6.0
• Supports multiple connections in L4 Layer and L4 segments
• Supports M-PHY HS data rates HS-Gear1 – Gear6, both A/B modes
• Supports CPort arbitration at both segment level and packet level
• Supports L2 data frames and control frames
• Supports up to two M-PHY lanes for UFS application
• Supports M-PHY RMMI (10,20,40,80 and 160) Interface in PHY layer
• Supports all power modes for M-PHY in PHY layer
• Supports all types of lane mapping (Lane 0 mapped to 1 etc)
• Supports link startup as per specs
• Supports maximum of 32 C-Ports
• Employs round robin arbitration across C-Ports
• Supports group acknowledgement of maximum 16 frames per traffic class
• Supports retransmission of frames
• Configurable buffer spaces
• Supports CSD, CSV
• Supports UniPro test feature
• TMPI support
• Supports CPort buffer based E2E checking
• Supports Scrambling as per specs
• Supports complete DME functionality
• Supports interrupt handling for the status of data transfer and error detection in the various layers of Unipro
• Supports below latest 2.0 Version features:
  • DME Reset Mode
  • Linkstartup sequence in HS Mode(HS G1A) or LS mode(PWM G1)
  • Supports PA capability user data in PACP CAP IND frame
  • Supports L2 buffer extension
  • Supports Extended save time
  • Supports HS-G5 Gear in HS Mode and removal of PWM Gears except PWM G1
  • Supports RMMI bus width extended to 80bits per lane interface in PHY Layer
  • Supports PA EOB Delay
  • Supports power mode change to only HS Gears and PWM gears are invalid when DME RESET mode is HS mode
• Supports below latest 3.0 version features:
  • Supports TFS
  • Supports Forward Error Correction and Detection
  • Supports ALIGN Pattern transmission and detection
  • Supports RMMI bus width extended to 160bits per lane interface in PHY Layer
• Supports PHY layer features:
  • Transmission and reception of encoded PHY symbols
  • Transmission of PHY IDLE symbols when no data is supplied
  • Detection of PHY IDLE symbols
  • Method to re-initialize the forward Link to overcome error situations
  • Provision of different power modes and a method to signal them from transmitter to receiver
• Supports PHY adapter layer features:
  • Transmission and reception of Data Link layer control symbols and data symbols via underlying PHY
  • Lane distribution and merging in multi-lane ports
  • Provision of MIPI UniPro power management operating modes
  • Re-Initialization of the PHY TX path
  • Transmit lane connect/disconnect features
  • One lane mapping to different lanes
  • PHY testing
  • Lane Data Path (LDP) processing based on Line coding
  • Link Equalization Training for HS Gears HS-G4 to HS-G6
• Supports Data Link layer features:
  • Frame composition and frame decomposition
  • Buffering Mechanism
  • Frame preemption
  • Triggering of PHY initialization
  • Two traffic classes by priority-based arbitration
  • Detect various protocol errors
• Supports Network layer features:
  • Addressing
  • Packet Composition and Packet Decomposition
  • Packet format recognition
  • Error handling
  • Support for one Traffic Class
  • Long Header trap to enable L3 and L4 extensions for future versions
• Supports Transport layer features:
  • Addressing
  • Segmentation and Reassembly
  • Segment Composition and segment decomposition
  • Segment format recognition
  • Connections management
  • End-to-End flow-control
  • Error handling
  • Different CPort arbitration algorithms supported

CORE: Core module interconnects all the sub-modules in the MIPI_Unipro IP. Ports of core module are the top level ports for the MIPI_Unipro IP.

DME: DME module handles the all TL, NL, DL and PA layer through Layer Management SAP. It updates the status of all four layers to Application layer.

UNIPRO TX: UNIPRO TX module performs the below operations,

Transport Layer performs the below operations,

• Accept the Data from Application layer into the segement buffers
• Appends TL header which has destination C Port id and ‘EOM’ bit
• Cport data segmentation
• E2E flow control
• Cport Arbitration

Network Layer performs the below operations,

• Accept the Payload from TL
• Appends NL header which has destination device id

Datalink Layer performs the below operations,

• Accepts the Payload with L4 & L3 Headers
• Form a complete frame with L4,L3,L2 Header, L2 Footer and CRC store it in Frame FIFO
• Two traffic classes by priority-based arbitration
• TX Preemption

PHY Adapter Layer performs the below operations,

• Accepts the control and data Symbols from DL Layer.
• Split the data on to the available lanes for transmission
• PACP frames transmission
• PHY Testing
• TX Lane Data Path (LDP) processing for both 8b10 and 1b1b Line coding

UNIPRO RX: UNIPRO RX module performs the below operations,

PHY Adapter Layer performs the below operations,

• Merge the data from the available lanes for reception
• Send the Control and Data Symbol to DL Layer
• PACP frames decode
• RX Lane Data Path (LDP) processing for both 8b10 and 1b1b Line coding

Datalink Layer performs the below operations,

• Accept the Payload with L4, L3, L2 Header, L2 Footer and CRC.
• Check for CRC and sequence number error
• RX Preemption
• Detect various protocol errors
• Send the Payload L4 and L3 Headers to NL

Network Layer performs the below operations,

• Check the Device Id and accept the data if Device Id is correct
• Send the Data with L4 header to TL

Transport Layer performs the below operations,

• Check the Cport id and TC
• Cport data Reassembly
• Routing of data to selected cport through Segment buffer

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.