ETHERNET SPEED BRIDGE IIP

• Compatible with IEEE 802.3-2022 standards for Ethernet technology 10M/100M/1000M
• Supports GMII and MII interfaces
• Supports for Full duplex and Half duplex mode
• Supports ICMP, IPV4, IPV6, ARP and UDP Packets of RFC standard
• Supports for 802.3.az Energy Efficient Ethernet(EEE)
• Supports 802.3.1Q and 802.3.1ad VLAN frames
• Supports for Control frame and Jumbo frame
• Supports for FCS (CRC) transmission and reception
• Supports for Pause frame based flow control in full duplex mode
• Supports for transmit and receive FIFO interface
• Supports Loopback Functionality
• Supports packet size from regular-size(as per the maximum frame length of Ethernet Packet) to Jumbo Packets(16k byte)
• Supports for programmable Inter Packet Gap(IPG) and Preamble length
• Supports VCD, FSDB waveform logging with remote configuration
• In house UNH compliance tested
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

CORE: Core module interconnects all the sub-modules in the ETHERNET 1G MAC IP. Ports of core module are the top level ports for the ETHERNET 1G MAC IP.

TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.

TX ASYNC FIFO: TX ASYNC FIFO module stores Transmitted data and process the data with the different read and write clock domain.

GMII/MII TX FSM: The TX FSM module receives the data from MAC client and maps them to the MAC 1G Interface by encapsulating the Ethernet packet and frame headers.

FLOW CTRL: Initiating the Transmission of pause frame based on the Receive FIFO's threshold or External requests.

PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.

GMII/MII RX FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.

RX ASYNC FIFO: RX ASYNC FIFO module stores Received data and process the data with the different read and write clock domain.

RX CTRL: Receive Control block processes the data from MAC 1G interface and push the data into RX ASYNC FIFO

MDIO: The MDIO Master serial interface is used to control the PHY registers with read and write frames.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

Transmit Buffer: The Transmit Buffer handles the Packet transmission from PHY to EMAC.

Receive Buffer: The Receiver Buffer handles the Packet transmission from EMAC to PHY.

Back Pressure: This module handles the generation of pause frame request logic when the transmit buffer is having the less space to store the data which has been received by HSMAC

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• SmartDV's Ethernet SPEED BRIDGE IP contains following
• The Ethernet interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.
• ISO26262 Safety Manual (SAM) Document
• ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document