NFC Controller IIP

• Implemented in Unencrypted Verilog, VHDL and SystemC
• Compliant with NFC Specification ISO/IEC 18092, ISO/IEC 14443, ISO/IEC 15693 and ECMA 340 standards.
• Complete NFC Controller PCD/PICC functionality.
• Support Half Duplex of operations.
• Supports all the four data rates.
• ->106 kbps
• ->212 kbps
• ->424 kbps
• ->848 kbps
• Supports two different kinds of communication modes.
• ->Active communication mode
• ->Passive communication mode
• Support both Type A and Type B.
• Supports the Multi Activation feature, which allows the Initiator to hold several Targets active simultaneously.
• Supports the chaining feature, which allows the Initiator or Target to transmit information that does not fit in a single block, by dividing the information into several blocks.
• Supports Configurable timing functions.
• ->Guard time
• ->Frame delay time
• ->Frame Waiting time
• ->Waiting Time extension
• Supports the following types of error detection.
• ->Sync error
• ->DID error
• ->Length error
• ->Acknowledgement error
• ->Invalid command error
• ->CRC error
• ->Parity error
• Re-transmission of corrupted messages.
• Supports to change the parameters(Transfer speed and Frame length) of PCD and PICC after the activation
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core module interconnects all the sub-modules in the NFC Controller IP. Ports of core module are the top level ports for the NFC Controller IP.

TFSM: TFSM module generates the NFC Controller IP transactions based on the commands received from CSR block. Also, based on the commands this module drives data to encoder module.

RFSM: RFSM module implements the NFC controller receiver state machine. This module is used to sample and store the frames.

RPRESCALER: RPrescaler module is used to divide the system clock based on the given rprescaler value to derive the serial clock input for reception of NFC Controller.

TPRESCALER: TPrescaler module is used to divide the system clock based on the given tprescaler value to derive the serial clock input for transmission of NFC Controller.

ENCODER: Encoder module is used to encode the input data and deliver the encoded data to the NFC Controller output. The encryption of the is based on the type of encoding used for type of protocol as per the standard specification.

DECODER: Decoder module is used to decode the input data and send the decoded data into the NFC Controller input. This module handles the decryption of the encrypted data.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.