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VDC-M Encoder IIP

VESA Display Compression-M Encoder IIP

VDC-M Encoder IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech VDC-M Encoder IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • VDC-M Version 1.2 Encoder
  • Fully compliant with the VDC-M Encoder Versions 1.1 and 1.2 specification and ensures standard-adherent operation across all supported configurations.
  • Supports any integer slice per line values.
  • Supports following maximum bitrates (BPPmax), as follows:
    • 3 × bits_per_component,for 4:4:4
    • 2 × bits_per_component,for 4:2:2
    • 1.5 × bits_per_component,for 4:2:0
  • Supports any combination of bits_per_pixel and slice_width.
  • Supports CSC(Color-space-conversion).
  • Supports the following Picture Hierarchy,
    • Block Level
    • Slice Level
    • Picture Level
  • Supports the following Encoder modes,
    • Transform Mode
    • BP Mode
    • MPP Mode
    • Fallback Modes
    • MPPF Mode
    • BP-SKIP Mode
  • Supports slice padding and the following types of slice padding,
    • Horizontal padding
    • Vertical padding
  • Supports all the following Flatness type detection,
    • Very flat
    • Somewhat flat
    • Complex-to-flat transition
    • Flat-to-complex transition
  • Supports rate control (RC) algorithm in the determination of QP.
  • Supports substream multiplexing.
  • Supports following Hadamard transform applied in the YCoCg color space,
    • 8-point Forward Hadamard Transform
    • 4-point Forward Hadamard Transform
  • Supports PPS decoding.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the VDC-M Encoder IP. Ports of core module are the top level ports for the VDC-M Encoder IP.

CSR: CSR contains all Control and Status Registers (CSRs). It decodes CPU-driven configuration commands and maps them to functional output signals across the IP.

CSC: CSC module converts input pixels from RGB to YCoCg-R to improve compression efficiency.

SLICE_BUFFER: Slice buffer module stores pixels for slice based processing, enabling low latency and independent encoding of each slice.

FLATNESS_CHECKER: Flatness checker module determines whether upcoming pixel groups are visually flat by analyzing pixel variation within a supergroup and generates a QP override to improve compression quality in low detail regions.

RATE_CONTROL: Rate control module controls bit allocation and quantization parameters to maintain constant output bit rate and buffer compliance.

TEST_AND_SELECT_MODE: Test and select mode module evaluates all coding modes per block, computes rate distortion cost, selects the best mode, and encodes the block using the selected mode.

LINE_BUFFER: Line buffer module holds reconstructed pixels from previous samples/lines to support spatial prediction.

ENTROPY_ENCODER: VLC module encodes quantized residuals and syntax elements using DSU-VLC to reduce bitstream size.

SUBSTREAM_MULTIPLEX: Substream multiplex module combines component substreams(Y, Co, Cg) into a single slice bitstream following DSC syntax.

RATE_BUFFER: Rate buffer module converts the variable length encoded output into a constant bit rate DSC bitstream suitable for transmission.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyPixel Clock FrequencyBitstream Clock Frequency
TSMC 28nm222.68K100MHz200MHz33.33MHz
UMSC 55nm443.45K100MHz200MHz33.33MHz
SMIC 40nm303.90K100MHz200MHz33.33MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyPixel Clock FrequencyBitstream Clock Frequency
AMD-xcvu9p-flga2104-2L-e37113 LUT's100MHz200MHz33.33MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.