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Sukshma-V1 Tiny RISC-V CPU

Ultra-Compact 32-bit Embedded Core

Sukshma-V1 Tiny RISC-V CPU

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Sukshma-V1 Tiny RISC-V CPU is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Versatile processor cores designed for everything from ultra-compact IoT sensors to high-performance edge computing. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High-Efficiency Pipeline: Advanced multi-stage pipelines optimized for maximum performance-per-watt, outpacing standard legacy architectures.

Scalable ISA: Full support for industry-standard instruction sets (8051, RISC-V) with modular extensions for floating-point, vectors, and security.

Functional Safety (ISO 26262): Available with ASIL-D ready features including hardware redundancy (DMR/TMR) and comprehensive fault-injection testing.

Advanced Debug & Trace: Integrated on-chip debugging solutions compatible with industry-standard development tools for rapid software bring-up.

FEATURES
  • Compliant with RISC-V RV32I or RV32E (16-register) base instruction sets.
  • Ultra-compact 2-stage in-order pipeline for minimal silicon area.
  • Extremely low power consumption: Advanced fine-grained clock gating.
  • Supports Machine-mode only for simplified, secure execution.
  • Optional Compressed (C) extension for superior code density.
  • Integrated Core Local Interrupt Controller (CLIC) for rapid response.
  • Standard AHB-Lite or APB system bus interfaces.
  • Smallest footprint in our RISC-V family (~15k gates).
FUNCTIONAL DESCRIPTION
ASIC AND FPGA IMPLEMENTATION
Process NodeFrequency (MHz)Area (Gates)
28nm HPC+600~15,500
40nm LP400~16,200
FPGA (Artix-7)150~800 LUTs

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.