The SivaKali Tech eSPI Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.
Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.
Proven Reliability: Thousands of production deployments ensuring rock-solid stability.
Driver Support: Includes bare-metal and Linux drivers to accelerate software development.
FEATURES
Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.6
Supports Single, Dual and Quad modes
Supports below system topologies,
Single Master - Single Slave
Single Master - Multiple Slave
Supports different types of resets as per spec,
eSPI reset from Master to Slave
eSPI reset from Slave to Master
Supports baud rate selection
Supports TX and RX operations as per specs
Supports below transaction phases
Command Phase
Turn-Around Phase
Response Phase
Supports below multiple channels
Peripheral Channel
Virtual Wires Channel
OOB Channel
Run-time Flash Access Channel
Supports CRC checking
Supports Direct Memory Access (Optional)
various kinds of errors detection and handling
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the Master IP. Ports of core module are the top level ports for the Master IP.
FSM: FSM module generates the eSPI transactions based on commands from CSR block. This blocks implements the features of eSPI spec.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for eSPI.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
SCK Clock Frequency
TSMC 28nm
11.43K
264MHz
66MHz
UMSC 55nm
20.09K
264MHz
66MHz
SMIC 40nm
12.18K
264MHz
66MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
