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USB3.x DEVICE IIP

Universal Serial Bus 3.2 Device IIP

USB3.x DEVICE IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech USB3.x DEVICE IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Perfect for consumer electronics, peripherals, and embedded IoT devices. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Certified Interoperability: Extensive testing against standard USB hosts and devices to guarantee plug-and-play compatibility.

Highly Configurable: Flexible endpoint configuration and FIFO sizing to optimize area vs. performance trade-offs.

Low Power Modes: Aggressive power management supporting Suspend/Resume and remote wakeup capabilities.

Legacy Support: Backward compatibility ensuring seamless operation with older USB revisions.

FEATURES
  • USB 3.x Common support
  • ->Compliant with USB 3.0/3.1/3.2 specification
  • ->Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2
  • ->Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
  • ->Configurable PIPE Interface width 8, 16 or 32 bits
  • ->Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)
  • ->Supports Interrupt/Bulk/Isochronous/Control Transfers
  • ->Control transfers supported by Endpoint 0
  • ->Separate Endpoint Buffers for IN bound and OUT bound packets
  • ->Supports lane polarity inversion
  • ->Supports Bulk Streaming
  • ->Supports extensible Host Controller Interface(xHCI)
  • ->Supports Scrambler/Descrambler
  • ->Option to enable/disable scrambling
  • ->CRC checking and generation
  • ->Supports Protocol Layer Error Handling.
  • ->Provides prioritized scheduling for periodic endpoints.
  • ->Supports PTM
  • ->Implements support for multiple outstanding IN transactions directed to different endpoints.
  • ->Implements Type 1 and 2 Buffers
  • ->Supports Master and Slave Loopback mode for PHY layer testing
  • ->Supports Compliance mode entry as per specification.
  • ->Supports USB Suspend state and supports remote wakeup devices.
  • ->Supports all SS/SSP Link Power Management States – U1, U2, U3
  • ->Support DMA (Optional)
  • ->Fully synthesizable.
  • ->Static synchronous design.
  • ->Positive edge clocking and no internal tri-states.
  • ->Scan test ready.
  • ->Simple host interfaces enable straightforward integration with microcontrollers and application processors USB 3.0
  • ->Supports Gen1 super speed with 5GT/s data rate
  • ->Supports single lane
  • ->Supports LCRD_A to LCRD_D Credits
  • USB 3.1
  • In addition to USB3.0 features,USB3.1 supports the following features
  • ->Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)
  • ->Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed
  • ->Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports
  • ->Supports SuperSpeedPlus Precision Time Measurement
  • ->Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet
  • ->Supports Length field replica
  • ->Supports Endpoint companion descriptor
  • ->Supports Type-A and Type-B credits
  • ->Supports 128B/132B Encoding/Decoding
  • USB 3.2
  • In addition to USB3.0 and USB3.1 features, USB 3.2 supports the following features.
  • ->Supports Dual lane
  • ->Supports Deskew buffer
  • ->Supports Data striping in dual lanes
  • ->Supports Configuration summary descriptor
  • ->Supports link error count and soft error count
  • Available as Additional Feature at extra cost
  • Support additional functionality of Vendor Specific Request
  • ISO26262 Automotive safety(ASIL B/D)
  • ->ISO26262 Safety Manual (SAM) Document
  • ->ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document
  • Memories with ECC
  • FPGA Validation
  • Customized SoC I/F
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the USB3.x Device IP. Ports of core module are the top level ports for the USB3.x Device IP.

CSR: The CSR (Control Status Register) has configuration of the Device IP. It is used for communication between firmware and RTL. The default configuration values and interrupt status are stored in CSR registers.

SCRAMBLER: Before transmission of the data, the data to be sent is scrambled in the scrambler based on LFSR value.

DESCRAMBLER: The received scrambled data is descrambled in this module.

EP0 PROCESSOR: The control transfer requests are processed in this module. From the Header Packet Decoder if the transfer type is control then the packet is passed to this module.

EP0 RAM ACCESS: The descriptor’s for the device is stored in this module. The main function of the module is to return descriptor value during enumeration.

IEP BUFFER: The payload to be transmitted are stored here. The IEP(In Endpoint) buffer facilitate data exchange from the DMA to host. The number of iep buffer changes based on number of endpoints.

OEP BUFFER: The payload received are stored here. The OEP(Out Endpoint) buffer facilitate data exchange from the host to DMA. The number of oep buffer changes based on number of endpoints.

DMA: DMA is used to offload the processor from moving data from Device to Memory for OUT transfer and also move data from memory to Device for IN transfer.

TIMER ENABLE: The Timer Enable module generates various timing pulses. In this module 100 ns pulse is generated using a counter. With 100ns pulse 1us,10us,100us,1ms and 10ms timer enable’s are generated.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic resourcesPIPE clock frequencyReference clock frequencyCore clock frequencySoC clock frequency
TSMC 28nm134.40K125MHz25MHz200MHz200MHz
UMSC 55nm279.94K125MHz25MHz200MHz200MHz
SMIC 40nm144.92K125MHz25MHz200MHz200MHz

FPGA Device and FamilyLogic resourcesPIPE clock frequencyReference clock frequencyCore clock frequencySoC clock frequency
AMD Virtex-7 FPGA(xc7vx485tffg1761-2)29987 LUT's125MHz25MHz200MHz200MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.