Skip to main content
REQUEST INFO
Skip to main content

GPIO IIP

GPIO IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech GPIO IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES
  • Compliant with standard protocol of GPIO specification
  • Supports single channel
  • Supports configurable channel width for GPIO pins from 1 to 32 bits
  • Supports dynamic programming of each GPIO bit as input or output
  • Supports dynamic programming of each GPIO drive strength
  • Supports dynamic programming of each GPIO to enable/disable pullup/pulldown
  • Supports dynamic programming of each GPIO to control trigger as level or edge
  • Supports dynamic programming of each GPIO to control trigger as active low or active high level trigger
  • Supports dynamic programming of each GPIO to control trigger as falling edge or rising edge trigger
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CSR: CSR module has the set of registers used to configure GPIO core, log the GPIO status, program the timeout value for Host and register to store the GPIO data.

CORE: Core module interconnects all the sub-modules in the Peripheral IP. Ports of core module are the top level ports for the Peripheral IP and the Core Module acts as the central interconnect hub.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 28nm4.70K100MHz
UMSC 55nm8.71K100MHz
SMIC 40nm4.89K100MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e14516 LUT's100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.