CORE: Core module interconnects all the sub-modules in the UFS Host Controller Interface IIP. Ports of core module are the top level ports for the UFS Host Controller Interface IIP
UFS REGISTER: UFS Register module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality
AXI READ AND WRITE SUB MASTERS: Axi Read and Write Submaster modules will initiates the read and write request to AXI master interface based on the information fetched from PRDT descriptor for Dataout and Datain UPIU's.Also initiate the write request to update the Completion status of Response UPIU.
UTP ENCODER: UTP Encoder module will encode the every fields for all UPIU's
LOOKUP TABLE: This module will store the information of UPIU's sent from host and used to clear the slot's after response received
COMMAND DECODER: Command Decoder module will decode the slot ID based on information from incoming UPIU's and clears the Doorbell
UTP DECODER: UTP Decoder module will decode the incoming UPIU's and identify the UPIU's based on transaction id received
RESPONSE PROCESSOR: Response Processor module will process the Response UPIU and update the command completion.
UIC PROCESSOR: UIC Processor module will be responsible for initiating UIC commands related to UniPro and track the status of UniPro
DATAOUT PROCESSOR: Dataout Processor module will pack the DATA OUT UPIU header based on received RTT UPIU informations and packs DATA OUT UPIU based on the data segment length from the respective PRDT Buffer space. It handles the Encryption of Dataout UPIU
DATAIN PROCESSOR: DATAIN Processor module will decode the incoming UPIU's and store them in respective PRDT buffer space and it handles the decryption of Datain UPIU
AXI Master: AXI Master module will initiated request to AXI Slave for both read and write transactions and performs the beat calculation, boundary cross check based on the requested ID for read request and write request
AXI Slave: AXI Slave module will initiate the write and read the registers of ufs register from AXI master
