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ARINC664 ES IIP

ARINC664 ES IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ARINC664 ES IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Fully Compliant with ARINC664 Part 7 (AFDX) Specification
  • Compliant with IEEE Standard 802.3-2022 Specification for MAC
  • Supports Full-duplex 10M/100M Ethernet interfaces
  • Supports MII/RMII Physical Layer device (PHY) Interfaces
  • Supports Redundancy Management in Transmitter and receiver
  • Supports integrity check of the Redundant packets
  • Supports up to 1024 Virtual Links (Configurable to 64K)
  • Hardware based BAG(Bandwidth Allocation Gap) enforcement (1ms to 128ms)
  • Jitter monitoring and policing (< 500us precision)
  • Max frame length (LMAX) enforcement per VL
  • Supports Round Robin traffic shaping
  • Shared memory architecture of 128 bit wide memory bus
  • Supports Virtual Link Traffic Shaping (BAG – Bandwidth Allocation Gap)
  • Ultra low latency and compact implementation
  • Supports IP/UDP packet handling with fragmentation and reassembler
  • Supports ICMP handling
  • Supports maximum size of IP/UDP packets up to 8KB (Most commonly used in all Aircraft systems)
  • Supports DMA engine for Transmit and Receive
  • Supports Programmable Inter Packet Gap(IPG) and Preamble length
  • FCS generation supported
  • Independent TX and RX Maximum Transmission Unit (MTU)
  • Configurable Transmit and Receive FIFOs
  • Provides detailed statistics as per the specification including VL (Virtual Link) message count
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • In house UNH compliance tested
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ARINC664 ES IP. Ports of core module are the top level ports for the ARINC664 ES IP.

TX DMA: DMA initiates the read request to the remote (host) memory and response from the remote memory is written in to the Local memory. When the DMA data transfer is completed the CPU is notified by issuing interrupt.

TX WRITE: Based on the TX lookup information, it forwards or drops the packets.

TX BUFFER: Tx buffer holds all packets received from TX write and send to TX fragment.

TX LOOKUP: TX lookup Receives information from CSR and sends the lookup table information output to the TX fragment.

TX LINK LIST: TX link list is used to provide grant for fetching new descriptor by using the round robin method.

TX FRAGMENT: Packet fragmentation logic is done by using the LMAX information.

TX ENCODER: Tx encoder packs and transmits a VL frame exactly at its scheduled transmission time.

TX SHAPER: TX shaper requests and provides slot to the tx fragment module after reading data from calendar memory.

TX REDUNDANCY: Based on the redudancy mode of VL, it will send data to mii_a and mii_b MAC modules.

TX MII: TX MII module adds header to the incoming frames and transmits the packets.

RX MII: The Rx MII module receives the Rx packet and extracts the VL, serial number and frame length and sends output to the Rx redundancy module.

RX LOOKUP: Rx lookup module store the RX lookup table informations which is shared by the user through CSR and accessed by RX redundancy for packet processing.

RX LINK LIST MANAGER: Rx link list manager module Provides grant for fetching new descriptor from rx fetch module.

RX REASSEMBLER: Rx reassembler implements the decapsulation of IP/UDP headers,reassembling of received packets and maintains the pointers. RX REASSEMBLER BUFFER: Rx Reassembler buffer module maintains the reassembled packets pointers till they are fully reassembled.

RX FETCH: Rx fetch module implements receiver descriptor fetching and it can provide it to link list manager whenever it request for the pointer.

RX BUFFER: Rx Buffer holds all packets received from reassembler and forward it to Rx send

RX SEND: RX send implements reading frame from buffer and sending to receive DMA

RX REDUNDANCY: Rx redundancy uses “First valid win”policy, which is first frame received from either A or B network with the next valid sequence number is accepted and passed to the receiving partition and its discards the second frame which is received with this same sequence number[Redundant].

RX DMA: DMA receive transfers the block of data from the local memory to the remote memory.

MDIO: The management interface is a simple two-wire, serial interface to connect management entity and a managed PHY for the purposes of controlling the PHY and gathering status from the PHY.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyMAC Clock Frequency
TSMC 28nm86.62K125MHz25MHz
UMSC 55nm191.62K125MHz25MHz
SMIC 40nm138.62K125MHz25MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyMAC Clock Frequency
xcku040-ffva1156-2-e8711 LUT's125MHz25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.