USB3.x OTG IIP

• USB 3.x Common support
• ->Compliant with USB 3.0/3.1/3.2/2.0 specification
• ->Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2
• ->Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
• ->Configurable PIPE Interface width 8, 16 or 32 bits
• ->Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)
• ->Supports Interrupt/Bulk/Isochronous/Control Transfers
• ->Control transfers supported by Endpoint 0
• ->Separate Endpoint Buffers for IN bound and OUT bound packets
• ->Supports lane polarity inversion
• ->Supports extensible Host Controller Interface(xHCI)
• ->Supports Scrambler/Descrambler
• ->Option to enable/disable scrambling
• ->Supports SS Bulk Streaming Endpoints, and USB 2.0 High Bandwidth Interrupt and Isochronous endpoints.
• ->Supports configurable endpoint characteristics – for Maximum Packet Size, Endpoint Type etc.
• ->CRC32 Checking and generation for SS Data and Header Packets.
• ->CRC16 checking and generation for HS/FS/LS data packets.
• ->CRC5 generation and checking for Tokens.
• ->Supports Split Transfers for FS/LS devices connected to HS Hubs while operating in Embedded Host Mode.
• ->Supports preamble for LS transfers while operating in Embedded Host Mode.
• ->Supports Protocol Layer Error Handling.
• ->Provides prioritized scheduling for periodic endpoints.
• ->Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.
• ->Supports USB Suspend state and supports remote wakeup devices.
• ->Supports all HS/FS USB Link Power Management States – L1, L2.
• ->Supports all SS USB Link Power Management States – U1, U2, and U3.
• ->Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.
• ->Support for clock gating and multi-power-well support.
• ->Supports USB 3.0 Link Power Management
• ->Support USB 2.0 LPM transactions.
• ->Supports USB 3.0 Loopack and Compliance Mode.
• ->Support USB 2.0 Test mode.
• ->Configurable number of Downstream ports for Embedded Host Applications.
• ->Supports multiple devices connected under SS/HS/FS hub for Embedded Host Applications
• USB 3.0
• ->Supports Gen1 super speed with 5GT/s data rate
• ->Supports single lane
• ->Supports ADP,HNP,SRP and RSP
• ->Supports LCRD_A to LCRD_D Credits
• USB 3.0 OTG
• ->Supported devices
• ->SS-OTG
• ->SSPC-OTG Devices
• ->SS-PO Devices
• ->SS-EH Devices
• ->Supported protocols
• ->SRP
• ->HNP
• ->ADP
• ->RSP for USB 3.0
• ->Supported speeds
• ->SS,HS and FS
• ->Supported feature selector
• ->b_hnp_enable
• ->a_hnp_support
• ->a_alt_hnp_support
• ->NTF_HOST_REL
• ->B3_RSP_ENABLE
• ->Support the all timeout condition
• ->a_wait_vfall_timout
• ->a_wait_vrise_timout
• ->a3_polling_tmout
• ->a3_recovery_tmout
• ->a3_rx_detect_active_tmout
• ->rsp_cnf_err_tmout
• ->rsp_ack_err_tmout
• ->rsp_wrst_err_timout
• ->b3_polling_tmout
• ->b3_recovery_tmout
• ->b3_rx_detect_active_tmout
• ->Combination of SSPC-OTG device communication
• ->SSPC-OTG device to SSPC-OTG device
• ->SSPC-OTG device to SS-OTG device
• ->SS-OTG device to SSPC-OTG device
• USB 3.1
• In addition to USB3.0 features,USB3.1 supports the following features
• ->Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)
• ->Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed
• ->Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports
• ->Supports SuperSpeedPlus Precision Time Measurement
• ->Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet
• ->Supports Length field replica
• ->Supports Endpoint companion descriptor
• ->Supports Type-A and Type-B credits
• ->Supports 128B/132B Encoding/Decoding
• USB 3.2
• In addition to USB 3.0 and USB 3.1 features, USB 3.2 supports the following features.
• ->Supports Dual lane
• ->Supports Deskew buffer
• ->Supports Data striping in dual lanes
• ->Supports Configuration summary descriptor
• ->Supports link error count and soft error count
• ->Supports retimer connectivity models
• ->Supports all the Retimer state machine states[RTSM]
• ->Supports SRIS and Bit-Level Retimers functionality
• ->Supports Retimer presence announcement through LBPM
• Support DMA (Optional)
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple host interfaces enable straightforward integration with microcontrollers and application processors
• Available as additional Feature at extra cost
• ->ISO26262 Functional safety(ASIL B/D)
• ->ISO26262 Safety Manual (SAM) Document
• ->ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document
• ->Memories with ECC
• ->FPGA Validation
• ->Customized SoC I/F

CORE: Core module interconnects all the sub-modules in the USB3.x OTG Controller IP. Ports of core module are the top level ports for the USB3.x OTG Controller IP.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

OTG FSM: OTG FSM module controls and automates role switching between host and device.

SRP: SRP(Session Request Protocol) module enables the device to request host for starting a new USB session when the VBUS is off.

SCRAMBLER: Before transmission of the data, the data to be sent is scrambled in the scrambler based on LFSR value.

DESCRAMBLER: The received scrambled data is descrambled in this module.

EP0 PROCESSOR: The control transfer requests are processed in this module. From the Header Packet Decoder if the transfer type is control then the packet is passed to this module.

EP0 RAM ACCESS: The descriptor’s for the device is stored in this module. The main function of the module is to return descriptor value during enumeration.

IEP BUFFER: The payload to be transmitted are stored here. The IEP buffer facilitate data exchange from the DMA to host. The number of iep buffer changes based on number of endpoints.

OEP BUFFER: The payload received are stored here. The OEP buffer facilitate data exchange from the host to DMA. The number of oep buffer changes based on number of endpoints.

DMA: DMA is used to offload the processor from moving data from Device to Memory for OUT transfer and also move data from memory to Device for IN transfer.

TIMER ENABLE: The Timer Enable module generates various timing pulses. In this module 100 ns pulse is generated using a counter. With 100ns pulse 1us,10us,100us,1ms and 10ms timer enable’s are generated.

TRANSACTION SCHEDULER: Transaction scheduler is responsible for deciding which USB trnasaction is issued next by the host.

TRANSACTOR: Transactor module performs the transactions selected by the transaction scheduler.

EVENT CONTROL: Event controls are used to generate,queue and report the events from the host controller to software.

COMMAND PROCESSOR: Command processor executes the xHCI commands issued by the software through command ring.

RX DATA FRAMER: Rx data framer is used to decode all the valid data coming from PHY.

TX/RX SYNC FIFO: Tx and Rx sync fifo's are used to send data or recieve data safely between different(CORE and PIPE) clocks.

LCW FRAMER: Lcw framer is used to frame the packets according to the specifications.

LC DECODER: Lc decoder is responsible for checking the received LCWs.

TX DATA BUFFER: Txdata framer is used to constructs the proper format of header packet.

CRC5/CRC16 GENERATOR/CHECKER: Crc5/16 generator/checker used to generate/check the CRC5 and CRC16 of the Link control word and Headpackets. LMP GENERATOR: Lmp generator is used to generate the LMP for link management and link control.

DATA PACKET DECODER: Data packet decode is used to identify and detects the errors in packet type.CRC check,sequence numbers.

CRC32 GENERATOR/CHECKER: Crc32 generator/checker used to generate/check the CRC32 for the payload of Datapackets.

LTSSM: LTSSM is is state machine controls the link behaviour between PHY and MAC.

OS GENERATOR/OS PROCESSOR: OS generator/processor is used to generate or process the Orderset information.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.