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FlexRay Controller IIP

Flexray Controller IIP

FlexRay Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech FlexRay Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Supports FLEXRAY Specification Version 3.0.1 and is compatible with version 2.1. Support Full Duplex of operations.
  • Complete FlexRay Transmitter/ Receiver functionality.
  • Supports cluster wakeup and startup.
  • Transmit and receive commands allow the user to transmit and receive FlexRay data.
  • Supports 2.5, 5 and 10 Mbit/s bitrate.
  • Support Bit alignment
  • All types of frame generation.
    • Static frames
    • Dynamic frames
  • Various kinds of Tx and Rx errors detection.
    • Syntax errors
    • Frame ID error (Frame ID = 0)
    • Header CRC error
    • CRC error
    • Over and undersize errors
    • Content errors
    • Cycle Count error
    • Frame ID error
    • Startup, Sync & Null frame errors w.r.t Dynamic segment
    • Startup & Sync frame errors w.r.t Static segment
    • Reception of Null frame
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the FLEXRAY Controller IP. Ports of core module are the top level ports for the Flexray Controller IP.

TFSM: TFSM Module is responsible for driving the Flexray frames through Bus.and also includes Transmition of Cluster Wakeup pattern,CAS(Collision Avoidance Symbol) and Frames(Data & NULL)

RFSM: RFSM Module is responsible for Sampling the Flexray frames through Bus.and also includes Reception of Cluster Wakeup pattern,CAS(Collision Avoidance Symbol) and Frames.

TIM: TIM Module is responsible for Bit timimg Characteristics(macrotick and microtick), and cycle generation based on segments(Static, Dynamic, Symbol window, NIT).

SUC: SUC Module is responisible for coldstart process of Flexray network.

CHI: CHI Module is responsible for controller host interface (CHI) command input from the firmware.

CHI_FRAME: CHI_FRAME module controls the handling of frame transmission based on the Input CHI command.

POC: POC(Protocol operation controller) module controls the operation of protocol.and implements The status of the controller.

TPRESCALER & RPRESCALER: These Modules are used to divide the system clock based on the given Prescaler value to derive the serial clock input for respective transmission and reception of Flexray controller.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 28nm56.31K80MHz
TSMC 12nm85.00K80MHz
TSMC 90nm81.88K80MHz
TSMC 130nm79.62K80MHz
TSMC 180nm85.98K80MHz
GF 180nm63.15K80MHz
SMIC 40nm60.36K80MHz
UMC 55nm96.93K80MHZ

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e9385 LUT's80MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.