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MIPI DEBUG UART Adaptor IIP

MIPI DEBUG UART Adaptor IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI DEBUG UART Adaptor IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES
  • Compliant with full Uart Adaptor functionality as per the MIPI Debug for I3C version 1.1.1.
  • Supports UART data byte packets as either 8 bit data or 7 bits of data with 1 bit of parity.
  • Supports all Debug CCC's and Opcodes.
  • Supports Error handling and flushing mechanism.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: CORE module interconnects all the sub-modules in the MIPI DEBUG UART Adaptor IIP (CSR, UART). Ports of core module are the top level ports for the MIPI DEBUG UART Adaptor IIP.

CSR : CSR module holds control, status, interrupt, configuration registers for the MIPI DEBUG UART Adaptor IIP which can be accessed via AMBA/Custom interface.

UART : UART module used to Receive the data from Network layer IB FIFO and Transmit the data to Network layer OB FIFO.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyNetwork Clock Frequency
TSMC 28nm18.07K800MHz800MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyNetwork Clock Frequency
AMD Virtex Ultrascale+51685 LUT's100MHz100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.