ETHERNET 40G MAC IIP

• Compliant with IEEE Standard 802.3-2022 specification clause 81
• Supports full duplex mode operation
• Supports XLGMII (Clause 81) interface
• Supports Programmable Inter Packet Gap(IPG) and Preamble length
• Supports MDIO and Clause 45 Interface
• Supports start control character alignment
• Provides detailed statistics as per the specification
• Supports Loopback functionality
• Supports Control frame and Jumbo Frame
• Supports transmit and receive FIFO interface
• Supports FCS(CRC) transmission and reception
• Supports Pause frame-based flow control
• Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
• Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
• Supports Wake-on-LAN support
• Supports AXI stream Interface for System Interface In house UNH compliance tested
• Optional support for TCP/IP
• Optional support for IEEE Standard 1588-2008 PTP
• Optional DMA support for both transmit and receive side
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core module interconnects all the sub-modules in the Ethernet 40G MAC IIP . Ports of core module are the top level ports for the Ethernet 40G MAC IIP.

TX-CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO. TX_FIFO : TX ASYNC FIFO module stores TX data and processes it with the different read and write clock domain.

Transmit MAC TX-FSM: The transmit FSM receives the data from MAC client and maps them to the MAC 40G Interface by encapsulating the Ethernet packet and frame headers.

Receive MAC RX-FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.

RX_FIFO : RX ASYNC FIFO module stores Rx data and process the data with the different read and write clock domain.

RX-CTRL: RX Control block processes the data from MAC 40G interface and push the data into Rx ASYNC FIFO.

MDIO: The MDIO Master serial interface is used to control the PHY registers with read and write frames

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.

FLOW CTRL: Initiating the Transmission of pause frame-based on the Receive FIFO's threshold or External requests.

LINK FAULT FSM: This block indicates the RX and TX link status, the local fault signal indicates by PHY layer.Local fault signal reached the RS layer, the RS continuously generate the remote fault signal on XLGMII TXD and TXC output signal

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.