CORE: Core module interconnects all the sub-modules in the SATA host controller IIP.Ports of core module are the top level ports for the SATA host controller IIP.
CSR: CSR Module has all the Control and Status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
APPS: Application module will generate the SATA commands based on the command registers in CSR module. Whenever the command is written by SoC interface in CSR module it will generate the internal interrupt to application layer. Based on the command application layer will generate the command and made request to transport layer for FIS generation and responses. Based on the SATA responses from the drive side it will update the error and status registers in CSR modules.
TRANSPORT: Transport module is responsible to generate the SATA frame as per request from the SATA apps layer. Once it receives request from the apps layer it will send the XRDY transmit request to SATA link layer. Once it gets the acknowledgement with RRDY it will send the frame with SOF, Data Dwords and EOF in the link.
LINK: Link module is responsible to transmit and receive frames, primitives based on control signals from the Transport layer, and received primitives or data‟s from the PHY layer.During data transmission it will also initiate and respond to flow control primitives and mechanisms. This module will also suppress the primitives using CONT primitives and also able to decode the suppressed primitives in the receiver link.
ENCODER: Encoder module is responsible for encoding 8 bit data into 10 bit data. Information to be transmitted over Serial ATA shall be encoded a byte (eight bits) at a time along with a data or control character indicator into a 10 bit encoded character and then sent serially bit by bit.
TBI_LOGIC: TBI Logic block is used to take encoded data and convert it to 10bits, 20bits, 40bits or 80bits stream data. This module will be available only when TBI interface is selected
SYNC_FSM: Sync fsm module is used to establish dword synchronization and monitors whether invalid dwords are received or not.
ELASTIC_FIFO: Elastice fifo module is used to compensate the difference in clock frequency between receiver clock and internally generated clock. It can able to handle + or - 175 Dword Frequency change either by adding/removing the deletable primitive. Hence this elastic FIFO prevents from data loss when overrun / underrun conditions occur.
DMA_PORT: DMA port module is used to transfer the data from system memory to Hard disk drive or writing the data to system memory when device Hard disk drive sends data in response with read command. Once it got the activation from the transport layer, it reads the command memory using the command base address and finds out the physical region descriptor address and count for the command. Based on the command type it reads/writes the data in system memory using the physical region descriptor address with the help of SoC master interface.
TBI_W_RX_OOB: OOB module is used to do phy oob initialization after reset condition. These OOB sequences bring the host controller to an initialized condition.
POWER_CONTROL_W_RX_OOB: Power control module is responsible for host controller to enter into low power mode when it reads data from the power management software register or it handles low power mode when device is initiated the request. To exit from the low power mode, comwake signal should be transmitted or received based on either host controller or device initiates the wake up request.
AHB_SLAVE: This AHB Slave module is used to write and read software registers.
AXI_SMASTER: AXI SMaster initiate write/read transfer based on the trigger signals from AXI SMaster control logic
