MIPI DSI-2 Transmitter IIP

• MIPI DSI-2 v2.2 Transmitter
• Fully compliant with the MIPI DSI-2 v2.2 specification and ensures standard-adherent operation across all supported configurations
• Supports full MIPI DSI-2 Transmitter functionality with DPHY v3.5
• Dynamically supports lane configurations up to 8 lanes
• Supports Data rate range from 80 Mbps to 9 Gbps per data lane
• Supports programmable parallel interface widths of 8bits, 16bits and 32bits
• Supports full MIPI DSI-2 Transmitter functionality with CPHY v2.1
• Dynamically supports lane configurations up to 8 lanes
• Supports Data rate range from 0.08 Gsps to 6 Gsps per trio
• Supports programmable parallel interface widths of 16bits, 32bits and 64bits
• Supports configurable output pixel processing of 1 pixel per clock
• Supports maximum resolution upto 8k@60Hz
• Compatible with the video formats which are mentioned in MIPI DSI-2 v2.2
• RGB 5:6:5(16 Bits Per Pixel)
• RGB 4:4:4(18,24,30,36,48 Bits Per Pixel)
• YCbCr 4:2:2(16,20,24 Bits Per Pixel)
• YCbCr 4:2:0(12 Bits Per Pixel)
• Integrates Error Correction Codes(ECC) and Cyclic Redundancy Checks(CRC)
• Compliant with dual MIPI DSI use case with VESA display stream compression(DSC)
• Supports burst and non burst mode transfer over DPI Interface
• Supports Bi-directional communication with fault recovery and contention
• Supports for ultra low power mode and escape mode
• Compliant with Adaptive Refresh Panel
• Compliant with Video Hybrid Mode
• Compliant with Scrambling
• Compliant with Skew Calibration
• Compliant with multiple independent data streams using 4 configurable virtual channels
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

DPI: The DPI interface Module converts pixel data into bytes and stores it in a FIFO.

DPIE: The DPI Event Generator generates display timing signals and sends the required sync packet.

DBI: The DBI Module manages command, read and write operations and selects high speed or low power transfer mode.

DCS: The DCS command module classifies commands as short or long packets.

RX UNPACKER: The RX Unpacker module extracts ECC, word count and data from reverse transfers and verifies the CRC.

ARBITER: The Arbiter module monitors the lane mode and allows the correct DBI packet based on high speed or low power operation.

CHANNELIZER: The Channelizer module shows when a DBI tranfer starts and ends.

LOW POWER CONTROL: The Low Power Control Module generates Escape mode and Ultra low power mode signals.

LOW POWER PACKER: The Low Power Packer Module adds calculated ECC and CRC to the data in Low power mode.

LOW POWER DATA TRANSMISSION: The Low Power Data Transmission Module indicates when low power data transfer is active.

PACKER: The Packer Module merges the header and data into one packet for high speed DPI and DBI transfer.

MAPPER: Mapper Module is used to map the output data across the active lanes.

SCRAMBLER: Scrambler Module is used to scramble the valid data bytes sent in a Long packet.

CSR: CSR module holds the registers and passes their values to the outputs.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.