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LIN Controller IIP

Local Interconnect Network Controller IIP

LIN Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech LIN Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Compliant with 2.2A LIN Specification
  • Full LIN transmit and receive functionality
  • Supports configurable master or slave functionality Supports all frame types
    • Unconditional frames
    • Event-triggered frames
    • Sporadic frames
    • Diagnostic frames
  • Supports programmable data rate between 1 kbps and 20 kbps
  • Supports programmable clock frequency up to 20 MHz
  • Supports 8-bit host controller interface
  • Supports cluster wake up and go to sleep command Supports LIN status management
  • Self-synchronization in slave nodes without quartz or ceramic resonators
  • Low cost single-wire implementation
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the LIN Controller IP. Ports of core module are the top level ports for the LIN Controller IP.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

UART: UART module implements UART transmit and receive logic

FSM: FSM module implements frame processor state machine. FSM module implement Header, response transmission and sampling.

CSYNC: Csync module implements the lin synchronizer

PRESCALER: Prescaler Module is used to divide the i_clk clock based on the given prescaler value to derive the serial clock for transmission and sampling of the frame.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 12nm16.68K20MHz
TSMC 28nm11.23K20MHz
TSMC 90nm15.80K20MHz
TSMC 130nm15.80K20MHz
TSMC 180nm16.87K20MHz
GF 180nm11.78K20MHz
SMIC 40nm11.98K20MHz
UMSC 55nm19.44K20MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e1872 LUT's20MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.