The SivaKali Tech AVSBUS Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with AVSBus specification as defined in version 1.3.1 Part III of PMBus Bus Specification
Supports HCI and Non HCI Interface
Full AVSBus Master Functionality
Supports 2-wire and 3-wire mode
Supports Multiple back to back frames and status for higher bus efficiency up to 256 Commands and responses
Supports all AVSBus Commands as per specification.
Supports all AVSBus Data types as per specification.
Support Clock Pausing between Command frames
Support Slave status response frames
Support Bus timeout function
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the Master IP. Ports of core module are the top level ports for the Master IP. AVSCLK clock is derived from i_clk based on prescaler value.
PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for AVSBUS. It is recommended that system clock be at least 4 times the desired AVSBus clock speed.
CSR: CSR module has all the control and status registers. Command and response storing is modled using 16 location memory for command and 16 location memory for response. It is possible to simplify and remove the memory.
MFSM: FSM module generates the AVSBus transcations on AVSBus based on commands from CSR block. This blocks implements all the features of AVSBus specs. Following are different types of frames supported by FSM block.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
AVS Clock Frequency
TSMC 12nm
10.83K
500MHz
50MHz
TSMC 28nm
6.28K
500MHz
50MHz
TSMC 90nm
10.41K
500MHz
50MHz
TSMC 130nm
10.41K
500MHz
50MHz
TSMC 180nm
12.63K
500MHz
50MHz
GF 180nm
8.23K
500MHz
50MHz
SMIC 40nm
6.81K
500MHz
50MHz
UMSC 55nm
16.07K
500MHz
50MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
1046 LUT's
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
