MIPI RFFE SPI Slave IIP

• Compliant with 3.0 MIPI RFFE Specification and SPI Block Guide V04.01 Specification
• Full MIPI RFFE Slave functionality
• Supports following frames,
• Command Frame
• Data/Address Frame
• No Response Frame
• Supports extended register read/writes
• Supports interrupt summary and identification command sequence
• Support Trigger and Extended trigger modes
• Support Masked write command sequence
• Supports Timed Trigger
• Supports Mappable Triggers
• Support Synchronous read
• Support Normal and Secondary operation mode
• Support USID Programming Procedure 1,2 and 3
• Support Group slave ID
• Supports device enumeration
• Supports Half-Speed Data Response (HSDR) Accesses
• Supports Full Command Sequence at Half-Speed SCLK
• Supports Delayed Read-back
• Supports Reserved Register Allocations in Basic Address Space (0x1C – 0x1F)
• Supports Reserved Register Allocations in Extended Address Space (0x20 – 0x3F)
• Supports Write Slave State via PWR_MODE bits
• Supports Read Slave State via PWR_MODE bits
• Supports Read PRODUCT_ID, MANUFACTURER_ID and USID from reserved registers
• Support Interrupt capable slave
• Supports Extended Frequency Range up to 52 MHz
• Supports the following Error detections
• Undefined command frame
• Command frame with parity error
• Command frame length error
• Address frame with parity error
• Data frame with parity error
• Read of unused register
• Write of an unused register
• Read using the broadcast ID or a GSID
• Full SPI Slave functionality
• Supports following frames for SPI
• Sleep Frame
• Wakeup Frame
• Write Frame
• Read Frame
• Supports 8 bit and 16 bit address for SPI
• Support single and burst transfer mode for SPI
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors
• Optionally this core can be built to have SPI or I2C interface for application where slave can have multiple interfaces like RFFE or SPI or I2C Interface
• This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

CORE: Core module interconnects all the sub-modules in the MIPI RFFE SPI Slave IP. Ports of core module are the top level ports for the MIPI RFFE SPI Slave IP.

START: Start module detects the Sequence Start Condition (SSC) on the RFFE bus. Start detect signal from this module triggers the FSM to collect and respond to transcations.

SDA OUT(Driver): Driver module is responsible for driving any data on RFFE bus from RTL Slave w.r.t i_scl clock reference.

FSM: This FSM trace the RFFE bus and receive the write data or respond to the read data.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.